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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12DJ3200QML-SP

現行

抗輻射保證 (RHA)、QMLV、300krad、12 位元、雙 3.2-GSPS 或單 6.4-GSPS ADC

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ADC12DJ3200QML-SP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (bit) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (bit) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA-FC (NWE) 196 225 mm² 15 x 15 CLGA-FC (ZMX) 196 225 mm² 15 x 15
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1 VPP-DIFF):
    • Dual-channel mode: –149.5 dBFS/Hz
    • Single-channel mode: –152.4 dBFS/Hz
  • Peak noise power ratio (NPR): 45.4 dB
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 7 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3 W
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1 VPP-DIFF):
    • Dual-channel mode: –149.5 dBFS/Hz
    • Single-channel mode: –152.4 dBFS/Hz
  • Peak noise power ratio (NPR): 45.4 dB
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 7 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3 W

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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類型 標題 日期
* Data sheet ADC12DJ3200QML-SP 6.4-GSPS, Single-Channel or 3.2-GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. B) PDF | HTML 2021年 3月 24日
* SMD ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 2020年 8月 4日
* Radiation & reliability report ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report 2020年 8月 3日
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012年 5月 4日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022年 11月 17日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
Technical article How SHP in plastic packaging addresses 3 key space application design challenges PDF | HTML 2022年 10月 17日
Selection guide TI Space Products (Rev. I) 2022年 3月 3日
EVM User's guide ADC12DJ3200EVMCVAL Evaluation Module User's Guide 2018年 1月 11日

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開發板

ADC12DJ3200EVM — ADC12DJ3200 12 位元雙路 3.2 GSPS 或單路 6.4 GSPS 射頻取樣 ADC 評估模組

ADC12DJ3200 評估模組 (EVM) 可用於評估裝置 ADC12DJ3200。ADC12DJ3200 是是一款具有緩衝類比輸入的低功耗、12 位元、雙 3.2-GSPS/單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC)，是具可編程 NCO 和降取設定 (包括未降取的 12 位元和 8 位元 ADC 輸出) 的整合式數位降壓轉換器，並且具有 JESD204B 介面。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。EVM 隨附 LMX2582 時鐘合成器和 LMK04828 JESD204B 時鐘產生器，可配置為提供適用於完整 JESD204B 子類別 1 (...)

使用指南: PDF
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開發板

ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP 評估模組

ADC12DJ3200EVMCVAL 是一款評估 ADC12DJ3200QML-SP 裝置的評估模組 (EVM)。ADC12DJ3200QML-SP 為航太級、低功耗、12位元、雙 3.2-GSPS/單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC)，具有緩衝類比輸入、整合式數位降壓轉換器和 JESD204B 介面。整合式數位降壓轉換器，搭載可編程 NCO 和降取設定，包括無降取 12 位元與 8 位元 ADC 輸出。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。板載 LMX2582 時鐘合成器和 LMK04832 JESD204B 時鐘產生器，可配置為提供完整 (...)

使用指南: PDF
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韌體

TI-JESD204-IP — JESD204 快速設計 IP，適用連接到 TI 高速資料轉換器的 FPGA

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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產品
高速 ADC (≥10 MSPS)
ADC12DJ3200QML-SP — 抗輻射保證 (RHA)、QMLV、300krad、12 位元、雙 3.2-GSPS 或單 6.4-GSPS ADC
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ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP 評估模組
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ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model

SLVMDV3.ZIP (47828 KB) - IBIS-AMI Model
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ADC12DJ3200QML-SP S-Parameter Model

SLVMDU7.ZIP (9 KB) - S-Parameter Model
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ADC12DJ3200QML-EVM Assembly Package

SLVRBF5.ZIP (4838 KB)
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ADC12DJ3200EVMCVAL Design Files

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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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