ADC12DJ5200SE
- ADC core:
- 12-bit resolution
- Up to 10.4GSPS in single-channel mode
- Up to 5.2GSPS in dual-channel mode
- Single Ended 50Ω Inputs:
- Analog input range (–3dB): 2 to 6.3GHz
- Full-scale input power (4.5GHz): - 1.25dBm
- Flexible VCM: AC coupled with no DC path to GND or supply
- Performance specifications:
- Noise floor (2.3GHz, –20dBFS,INPUTFS = 1.5dBm):
- Dual-channel mode: –149dBFS/Hz
- Single-channel mode: –151.5dBFS/Hz
- ENOB (dual channel, FIN = 2.3GHz): 8.5 Bits
- Noise floor (2.3GHz, –20dBFS,INPUTFS = 1.5dBm):
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Optional digital down-converters (DDC):
- 4x, 8x, 16x and 32x complex decimation
- Four independent 32-Bit NCOs per DDC
- Peak RF Input Power: +26.25dBm (+ 27.5dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 4W
- Power supplies: 1.1V, 1.9V
The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3dB input frequency range of 2 to 6.3GHz enables direct RF sampling of S-band and C-band for frequency agile systems.
The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ADC12DJ5200SE 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) with Integrated Baluns datasheet (Rev. C) | PDF | HTML | 2025年 4月 8日 |
| Application note | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025年 3月 28日 | |
| Application note | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025年 3月 26日 |
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|---|---|---|
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