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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

AM3358-EP

現行

Sitara 處理器：Arm Cortex-A8、3D、PRU-ICSS、HiRel、CAN

立即訂購
產品規格表

AM3358-EP

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A8 Frequency (MHz) 800 Graphics acceleration 1 3D Display type 1 LCD Protocols Ethernet, ICSS, Profibus, Profinet Features General purpose Operating system Linux, RTOS Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 800 Graphics acceleration 1 3D Display type 1 LCD Protocols Ethernet, ICSS, Profibus, Profinet Features General purpose Operating system Linux, RTOS Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 105
NFBGA (GCZ) 324 225 mm² (15 mm × 15 mm)
  • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor
    • NEON™ SIMD coprocessor
    • 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
    • 256KB of L2 cache with error correcting code (ECC)
    • 176KB of on-chip boot ROM
    • 64KB of dedicated RAM
    • Emulation and debug - JTAG
    • Interrupt controller (up to 128 interrupt requests)
  • On-chip memory (shared L3 RAM)
    • 64KB of general-purpose on-chip memory controller (OCMC) RAM
    • Accessible to all masters
    • Supports retention for fast wakeup
  • External memory interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
      • mDDR: 200-MHz clock (400-MHz data rate)
      • DDR2: 266-MHz clock (532-MHz data rate)
      • DDR3: 400-MHz clock (800-MHz data rate)
      • DDR3L: 400-MHz clock (800-MHz data rate)
      • 16-bit data bus
      • 1GB of total addressable space
      • Supports one x16 or two x8 memory device configurations
    • General-purpose memory controller (GPMC)
      • Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH code to support 4-, 8-, or 16-bit ECC
      • Uses hamming code to support 1-bit ECC
    • Error locator module (ELM)
      • Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
  • Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
    • Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
    • Two programmable real-time units (PRUs)
      • 32-bit load/store RISC processor capable of running at 200 MHz
      • 8KB of instruction RAM with single-error detection (parity)
      • 8KB of data RAM with single-error detection (parity)
      • Single-cycle 32-bit multiplier with 64-bit accumulator
      • Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
    • 12KB of shared RAM with single-error detection (parity)
    • Three 120-byte register banks accessible by each PRU
    • Interrupt controller (INTC) for handling system input events
    • Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
    • Peripherals inside the PRU-ICSS:
      • One UART port with flow control pins, supports up to 12 Mbps
      • One enhanced capture (eCAP) module
      • Two MII Ethernet ports that support industrial ethernet
      • One MDIO port
  • Power, reset, and clock management (PRCM) module
    • Controls the entry and exit of stand-by and deep-sleep modes
    • Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
    • Clocks
      • Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
      • Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
      • Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
    • Power
      • Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
      • Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
      • Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
      • Dynamic voltage frequency scaling (DVFS)
  • Real-time clock (RTC)
    • Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
    • Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
    • Independent power-on-reset (RTC_PWRONRSTn) input
    • Dedicated input pin (EXT_WAKEUP) for external wake events
    • Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
    • Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
  • Peripherals
    • Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
    • Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
      • Integrated switch
      • Each MAC supports MII, RMII, RGMII, and MDIO interfaces
      • Ethernet MACs and switch can operate independent of other functions
      • IEEE 1588v2 precision time protocol (PTP)
    • Up to two controller-area network (CAN) ports
      • Supports CAN version 2 parts A and B
    • Up to two multichannel audio serial ports (McASPs)
      • Transmit and receive clocks up to 50 MHz
      • Up to four serial data pins per McASP port with independent TX and RX clocks
      • Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
      • Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
      • FIFO buffers for transmit and receive (256 bytes)
    • Up to six UARTs
      • All UARTs support IrDA and CIR modes
      • All UARTs support RTS and CTS flow control
      • UART1 supports full modem control
    • Up to two master and slave McSPI serial interfaces
      • Up to two chip selects
      • Up to 48 MHz
    • Up to three MMC, SD, SDIO ports
      • 1-, 4-, and 8-bit MMC, SD, SDIO modes
      • MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
      • Up to 48-MHz data transfer rate
      • Supports card detect and write protect
      • Complies with MMC4.3, SD, SDIO 2.0 specifications
    • Up to three I2C master and slave interfaces
      • Standard mode (up to 100 kHz)
      • Fast mode (up to 400 kHz)
    • Up to four banks of general-purpose I/O (GPIO) pins
      • 32 GPIO pins per bank (multiplexed with other functional pins)
      • GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
    • Up to three external DMA event inputs that can also be used as interrupt inputs
    • Eight 32-bit general-purpose timers
      • DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
      • DMTIMER4–DMTIMER7 are pinned out
    • One watchdog timer
    • SGX530 3D graphics engine
      • Tile-based architecture delivering up to 20 million polygons per second
      • Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
      • Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-grained task switching, load balancing, and power management
      • Advanced geometry DMA-driven operation for minimum CPU interaction
      • Programmable high-quality image anti-aliasing
      • Fully virtualized memory addressing for OS operation in a unified memory architecture
    • LCD controller
      • Up to 24-bit data output; 8 bits per pixel (RGB)
      • Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
      • Integrated LCD interface display driver (LIDD) controller
      • Integrated raster controller
      • Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
      • 512-word deep internal FIFO
      • Supported display types:
        • Character displays - uses LIDD controller to program these displays
        • Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
        • Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
    • 12-bit successive approximation register (SAR) ADC
      • 200K samples per second
      • Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
      • Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
    • Up to three 32-bit eCAP modules
      • Configurable as three capture inputs or three auxiliary PWM outputs
    • Up to three enhanced high-resolution PWM modules (eHRPWMs)
      • Dedicated 16-bit time-base counter with time and frequency controls
      • Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
    • Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
  • Device identification
    • Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
      • Production ID
      • Device part number (unique JTAG ID)
      • Device revision (readable by host ARM)
  • Debug interface support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
    • Supports device boundary scan
    • Supports IEEE 1500
  • DMA
    • On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
      • Transfers to and from on-chip memories
      • Transfers to and from external storage (EMIF, GPMC, slave peripherals)
  • Inter-processor communication (IPC)
    • Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox registers that generate interrupts
        • Initiators (Cortex-A8, PRCM)
      • Spinlock has 128 software-assigned lock registers
  • Security
    • Crypto hardware accelerators (AES, SHA, PKA, RNG)
  • Boot modes
    • Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
  • Package:
    • 324-pin S-PBGA-N324 package
      (GCZ suffix), 0.80-mm ball pitch
  • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor
    • NEON™ SIMD coprocessor
    • 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
    • 256KB of L2 cache with error correcting code (ECC)
    • 176KB of on-chip boot ROM
    • 64KB of dedicated RAM
    • Emulation and debug - JTAG
    • Interrupt controller (up to 128 interrupt requests)
  • On-chip memory (shared L3 RAM)
    • 64KB of general-purpose on-chip memory controller (OCMC) RAM
    • Accessible to all masters
    • Supports retention for fast wakeup
  • External memory interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
      • mDDR: 200-MHz clock (400-MHz data rate)
      • DDR2: 266-MHz clock (532-MHz data rate)
      • DDR3: 400-MHz clock (800-MHz data rate)
      • DDR3L: 400-MHz clock (800-MHz data rate)
      • 16-bit data bus
      • 1GB of total addressable space
      • Supports one x16 or two x8 memory device configurations
    • General-purpose memory controller (GPMC)
      • Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH code to support 4-, 8-, or 16-bit ECC
      • Uses hamming code to support 1-bit ECC
    • Error locator module (ELM)
      • Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
  • Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
    • Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
    • Two programmable real-time units (PRUs)
      • 32-bit load/store RISC processor capable of running at 200 MHz
      • 8KB of instruction RAM with single-error detection (parity)
      • 8KB of data RAM with single-error detection (parity)
      • Single-cycle 32-bit multiplier with 64-bit accumulator
      • Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
    • 12KB of shared RAM with single-error detection (parity)
    • Three 120-byte register banks accessible by each PRU
    • Interrupt controller (INTC) for handling system input events
    • Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
    • Peripherals inside the PRU-ICSS:
      • One UART port with flow control pins, supports up to 12 Mbps
      • One enhanced capture (eCAP) module
      • Two MII Ethernet ports that support industrial ethernet
      • One MDIO port
  • Power, reset, and clock management (PRCM) module
    • Controls the entry and exit of stand-by and deep-sleep modes
    • Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
    • Clocks
      • Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
      • Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
      • Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
    • Power
      • Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
      • Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
      • Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
      • Dynamic voltage frequency scaling (DVFS)
  • Real-time clock (RTC)
    • Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
    • Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
    • Independent power-on-reset (RTC_PWRONRSTn) input
    • Dedicated input pin (EXT_WAKEUP) for external wake events
    • Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
    • Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
  • Peripherals
    • Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
    • Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
      • Integrated switch
      • Each MAC supports MII, RMII, RGMII, and MDIO interfaces
      • Ethernet MACs and switch can operate independent of other functions
      • IEEE 1588v2 precision time protocol (PTP)
    • Up to two controller-area network (CAN) ports
      • Supports CAN version 2 parts A and B
    • Up to two multichannel audio serial ports (McASPs)
      • Transmit and receive clocks up to 50 MHz
      • Up to four serial data pins per McASP port with independent TX and RX clocks
      • Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
      • Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
      • FIFO buffers for transmit and receive (256 bytes)
    • Up to six UARTs
      • All UARTs support IrDA and CIR modes
      • All UARTs support RTS and CTS flow control
      • UART1 supports full modem control
    • Up to two master and slave McSPI serial interfaces
      • Up to two chip selects
      • Up to 48 MHz
    • Up to three MMC, SD, SDIO ports
      • 1-, 4-, and 8-bit MMC, SD, SDIO modes
      • MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
      • Up to 48-MHz data transfer rate
      • Supports card detect and write protect
      • Complies with MMC4.3, SD, SDIO 2.0 specifications
    • Up to three I2C master and slave interfaces
      • Standard mode (up to 100 kHz)
      • Fast mode (up to 400 kHz)
    • Up to four banks of general-purpose I/O (GPIO) pins
      • 32 GPIO pins per bank (multiplexed with other functional pins)
      • GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
    • Up to three external DMA event inputs that can also be used as interrupt inputs
    • Eight 32-bit general-purpose timers
      • DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
      • DMTIMER4–DMTIMER7 are pinned out
    • One watchdog timer
    • SGX530 3D graphics engine
      • Tile-based architecture delivering up to 20 million polygons per second
      • Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
      • Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-grained task switching, load balancing, and power management
      • Advanced geometry DMA-driven operation for minimum CPU interaction
      • Programmable high-quality image anti-aliasing
      • Fully virtualized memory addressing for OS operation in a unified memory architecture
    • LCD controller
      • Up to 24-bit data output; 8 bits per pixel (RGB)
      • Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
      • Integrated LCD interface display driver (LIDD) controller
      • Integrated raster controller
      • Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
      • 512-word deep internal FIFO
      • Supported display types:
        • Character displays - uses LIDD controller to program these displays
        • Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
        • Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
    • 12-bit successive approximation register (SAR) ADC
      • 200K samples per second
      • Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
      • Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
    • Up to three 32-bit eCAP modules
      • Configurable as three capture inputs or three auxiliary PWM outputs
    • Up to three enhanced high-resolution PWM modules (eHRPWMs)
      • Dedicated 16-bit time-base counter with time and frequency controls
      • Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
    • Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
  • Device identification
    • Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
      • Production ID
      • Device part number (unique JTAG ID)
      • Device revision (readable by host ARM)
  • Debug interface support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
    • Supports device boundary scan
    • Supports IEEE 1500
  • DMA
    • On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
      • Transfers to and from on-chip memories
      • Transfers to and from external storage (EMIF, GPMC, slave peripherals)
  • Inter-processor communication (IPC)
    • Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox registers that generate interrupts
        • Initiators (Cortex-A8, PRCM)
      • Spinlock has 128 software-assigned lock registers
  • Security
    • Crypto hardware accelerators (AES, SHA, PKA, RNG)
  • Boot modes
    • Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
  • Package:
    • 324-pin S-PBGA-N324 package
      (GCZ suffix), 0.80-mm ball pitch

The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 AM3358-EP Sitara™ Processor datasheet (Rev. B) PDF | HTML 2019/4/18
* 勘誤表 AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) 2017/1/3
* 輻射及可靠性報告 AM3358BGCZA80EP Reliability Report 2015/12/17
* VID AM3358-EP VID V6215602 2016/6/21
應用說明 Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025/11/24
白皮書 Securing Arm-Based Application Processors (Rev. F) PDF | HTML 2025/2/26
白皮書 Time Sensitive Networking for Industrial Automation (Rev. C) PDF | HTML 2023/7/31
應用說明 Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023/5/24
應用說明 High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/2/24
設計指南 Discrete Power Solution for AM335x in 12mmx12mm Form-Factor Reference Design (Rev. A) PDF | HTML 2021/11/9
應用說明 Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) 2021/5/7
更多文件說明 From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020/12/16
白皮書 EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020/7/28
應用說明 AM335x Schematic Checklist (Rev. A) PDF | HTML 2019/12/19
使用指南 AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 2019/12/13
應用說明 Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 2019/9/13
Product overview Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) 2019/7/30
白皮書 Power optimization techniques for energy-efficient systems (Rev. A) 2019/6/28
應用說明 AM335x Hardware Design Guide PDF | HTML 2019/5/3
使用指南 Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 PDF | HTML 2019/4/11
應用說明 Common EOS pitfalls in board design PDF | HTML 2019/2/13
應用說明 McASP Design Guide - Tips, Tricks, and Practical Examples 2019/1/10
應用說明 PRU Read Latencies (Rev. A) 2018/12/21
白皮書 Ensuring real-time predictability (Rev. B) 2018/12/4
應用說明 PRU-ICSS EtherCAT Slave Troubleshooting Guide 2018/11/7
應用說明 PRU-ICSS / PRU_ICSSG Migration Guide PDF | HTML 2018/11/5
使用指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018/9/24
應用說明 Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) 2018/3/28
使用指南 Powering the AM335x With the TPS650250 (Rev. B) 2018/3/14
白皮書 Data concentrators: The core of energy and data management (Rev. A) 2018/2/21
白皮書 POWERLINK on TI Sitara Processors (Rev. A) 2018/1/10
Product overview TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) 2017/12/19
使用指南 TPS65910Ax User's Guide for AM335x Processors (Rev. F) 2017/12/8
應用說明 AM335x Reliability Considerations in PLC Applications (Rev. A) 2017/4/27
白皮書 Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 2016/8/11
白皮書 Building automation for enhanced energy and operational efficiency (Rev. A) 2015/10/26
白皮書 Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) 2015/3/3
使用指南 G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide 2014/11/13
使用指南 Powering the AM335x with the TPS65217x . (Rev. I) 2014/9/6
白皮書 Mainline Linux™ ensures stability and innovation 2014/3/27
白皮書 Linaro Speeds Development in TI Linux SDKs PDF | HTML 2013/8/27
白皮書 The Yocto Project:Changing the way embedded Linux software solutions are develop 2013/3/14
白皮書 Smart thermostats are a cool addition to the connected home 2012/9/27

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TMDSICE3359 — AM3359 工業通訊引擎

The AM3359 Industrial Communications Engine (ICE) is a development platform targeted for systems that specifically focus on the industrial communications capabilities of the Sitara AM335x Arm® Cortex™-A8 processors.

The AM335x Arm Cortex-A8 processors integrate the Programmable Real-time Unit (PRU) (...)

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開發板

TMDXEVM3358 — AM335x 評估模組

The AM335x Evaluation Module (EVM) enables developers to immediately start evaluating the AM335x processor family (AM3351, AM3352, AM3354, AM3356, AM3358) and begin building applications for factory automation, building automation, grid infrastructure, and more.

使用指南: PDF
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開發板

TPS65217CEVM — TPS65217C 評估模組

The TPS65217CEVM is a fully assembled platform for evaluating the performance of the TPS65217C power management device.

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開發板

TPS65218EVM-100 — TPS65218 評估模組

TPS65218EVM 是一個已完成組裝的平台，用於評估 TPS65218 電源管理裝置的性能。

使用指南: PDF | HTML
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開發板

ADVAN-3P-SITARA-SOMS — Advantech Sitara SOM 和 SBCS

Advantech offers Sitara™ based embedded core computing solutions including computer-on-modules, single-board-computers and box computers. Their compact, low-power-consumption, and cost-effective Arm®-based platform solutions are designed to deliver easier system integration, better (...)
從：Advantech
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開發板

BYTES-3P-SITARASOMS — 工作位元組 Sitara SOM

bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


從：bytes at work AG
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開發板

COMPU-3P-SITARASOMS — Compulab Sitara SOM

CompuLab is a leading manufacturer of computer-on-module boards and miniature PC systems. CompuLab's products excel with an advanced set of features, outstanding level of integration, high reliability and affordable prices. Annual manufacturing rate of over 100,000 boards and systems positions (...)
從：CompuLab
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開發板

CRLNK-3P-SOMS — 適用於 TI ARM 架構處理器的 Critical Link MitySOM 系統模組

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

從：Critical Link LLC
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開發板

FORLX-3P-SITARA-SOMS — Forlinx Sitara SOM

As a member unit of CSIA (China Software Industry Association) Embedded System Branch, Forlinx Embedded Tech Co., Ltd. has the capability to design, prototype and manufacture printed circuit boards, sub-assemblies and complete electronic products. Forlinx is committed to the development of Sitara (...)
從：Forlinx Embedded Tech. Co., Ltd
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開發板

MYIR-3P-SITARASOMS — MYIR Sitara SOM

MYIR offers a series of development kits and system-on-modules based on TI's AM335x Arm® Cortex®-A8 processors to meet customers' different requirements. MYIR also offers a compact single board computer Rico board based on TI's newest AM437x Arm Cortex-A9 solution. MYIR also offers custom (...)
從：MYIR Tech Limited
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開發板

OCTVO-3P-AM335X — Octavo Systems AM335x 型系統級封裝

Octavo Systems 是為全球創新者提供系統級封裝 (SIP) 架構解決方案的領導者。OSD335x 系列 SiP 裝置是基於德州儀器的 Sitara™ AM335x Arm® Cortex®-A8 處理器開發和部署高效能嵌入式系統的最快速且最具成本效益的方法。

OSD335x 裝置整合執行速度高達 1GHz 的 Sitara™ AM335x Arm® Cortex®-A8 處理器，以及高達 1GB 的 DDR3、TPS65217C 電源管理 IC、TL5209 LDO、EEPROM（選用）、eMMC（選用）、MEMS 振盪器（選用）和被動元件，成為一個易於使用的 BGA 封裝。

(...)

從：Octavo Systems
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開發板

PHYTC-3P-PHYBOARD-AM335X — 適用 AM335x Arm® 架構 Sitara™ 處理器的 PHYTEC® phyBOARD®-AM335x 開發套件

phyBOARD®-AM335x 配備 TI Sitara™ AM335x 為基礎的 phyCORE-AM335x 系統模組 (SOM)，直接焊接在載板 PCB 上。SOM 與載板間的「直接焊接連接 (DSC)」可省略板與板連接器來降低系統成本。phyBOARD 採用 Pico-ITX 尺寸，非常適合部署在各種強大的工業應用中。

PHYTEC 是能讓客戶快速且輕易的將複雜產品導入市場的領先業界系統模組 (SOM)、嵌入式中介軟體和設計服務提供者及整合商。我們利用博深的領域專業、高品質產品、供應鏈專業及敏捷的共同作業實務，從設計到生產逐步引導客戶。PHYTEC (...)

從：PHYTEC
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開發板

TQ-3P-SITARASOMS — 適用於 TI Arm 架構處理器和微控制器的 TQ Group 系統模組

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
從：TQ-Group
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開發板

VANWS-3P-VGATEWAY — 來自基於 AM335x 的 Vanteon 無線解決方案的 vGATEWAY 參考設計

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

從：Vanteon Wireless Solutions
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開發板

VAR-3P-SITARASOMS — Variscite Sitara SOM

Variscite designs and produces a variety of system on modules and single board computers based TI's Sitara™, OMAP™ and DaVinci™ processors, covering a wide range of products, segments and markets. Variscite provides its customers with a complete development kit supporting Windows (...)
從：Variscite
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子卡

PRUCAPE — TI PRU Cape

TI PRU Cape 是 BeagleBone Black 附加電路板，可讓使用者了解 TI 強大的可編程即時單元 (PRU) 核心及基本功能。PRU 是整合在 Sitara AM335x 和 AM437x 裝置系列中的低延遲微控制器子系統。  PRU 核心針對確定性、即時處理、直接存取 I/O 與超低延遲需求進行最佳化。  它包括適用於 GPIO、音訊和溫度感測器的 LED 和按鈕。  BeagleBone Black 與 PRUCAPE 搭配使用，是在 Sitara 平台上開始進行 PRU 開發的理想 EVM 解決方案。

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。  請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。  對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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軟體開發套件 (SDK)

PROCESSOR-SDK-AM335X — 適用於 AM335x Sitara 處理器的處理器 SDK - 支援 Linux 和 TI-RTOS

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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軟體開發套件 (SDK)

TIBLUETOOTHSTACK-SDK — TI 雙模式 Bluetooth® 堆疊

TI 的雙模式 Bluetooth 堆疊支援 Bluetooth + Bluetooth 低功耗，並包含實作 Bluetooth 4.0/4.1/4.2 規格的單模式與雙模式產品。Bluetooth 堆疊已完全通過 Bluetooth 技術聯盟 (SIG) 認證並免權利金，提供簡易的命令行範例應用程式以加速開發，並且根據需求提供 MFI 功能。

堆疊可與以下裝置配合使用：

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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作業系統 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
從：Mentor Graphics Corporation
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作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS，專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構，能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
從：QNX
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驅動程式或資料庫

PRU-ICSS-INDUSTRIAL-SW — 適用於 Sitara™ 處理器的 PRU-ICSS 工業軟體

PRU-ICSS 通訊協定為 TI Sitara 處理器實現即時工業通訊。  PRU-ICSS 通訊協定可在 Processor-SDK-RTOS、TI 的統合軟體開發平台上使用，並且包含最佳化 PRU-ICSS 韌體，這是適用於 ARM 處理器及範例應用的對應 PRU-ICSS 驅動程式。PRU-ICSS 韌體在 PRU 核心上運作，將時間關鍵的鏈路層處理從運作 TI-RTOS 的主 ARM 處理器中卸載。PRU-ICSS 驅動程式為 PRU-ICSS 資源提供了簡單的存取方式，並能輕鬆與在 ARM 核心上運作的通訊協定堆疊和應用程式軟體整合。  (...)

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驅動程式或資料庫

TI-15.4-STACK-GATEWAY-LINUX-SDK — TI 15.4 堆疊閘道 Linux 軟體開發套件

The TI-15.4-Stack-Gateway-Linux Software Development Kit (SDK) provides a Linux software middleware for the TI 15.4-Stack companion solution. It includes a full Linux user-space software that runs on top of the TI Processor SDK for AM335x platform, which interfaces with the co-processor embedded (...)

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驅動程式或資料庫

WIND-3P-VXWORKS-LINUX-OS — Wind River 處理器 VxWorks 和 Linux 作業系統

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)

從：Wind River Systems
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驅動程式或資料庫

WIT-3P-SITARABSP — Witekio Sitara Android 和 Windows 作業系統

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
從：Witekio
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軟體程式設計工具

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。  

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軟體程式設計工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash 是 TI 龐大 CCStudio™ 開發生態系統的一部分，是一款用於在 TI 微控制器與無線連線裝置上對晶片內快閃記憶體進行燒錄，以及在 TI 處理器上對板載快閃記憶體進行燒錄的軟體工具。UniFlash 提供圖形化介面與命令行介面，並可在桌面上或雲端中執行。

UniFlash 可從 CCStudio™ 開發人員區上的雲端執行，或在下載後於 Windows®、Linux® 和 macOS® 電腦中使用。

請注意，mmWave、AMx、K2G 和 J7 裝置不支援 macOS。AMx、K2G 和 J7 裝置僅於命令列上支援。

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支援軟體

AUTOMATA-3P-INDUSTRIALCOMMS — Cannon Automata Sercos III

The Sercos III Slave Communiction Stack allows to implement the Real-time Ethernet protocol Sercos III for any kind of slave devices. The source code includes SCP (Sercos Communication Profile) and GDP (General Device Profile). In addition, the stack already includes many optional function classes (...)
從：AUTOMATA
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模擬型號

AM335x Thermal Model

SPRM824.ZIP (10 KB) - 熱模型
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模擬型號

AM335x ZCE IBIS Model (Rev. B)

SPRM556B.ZIP (21124 KB) - IBIS 模型
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模擬型號

AM335x ZCE Rev. 2.0 BSDL Model (Rev. A)

SPRM548A.ZIP (8 KB) - BSDL 模型
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模擬型號

AM335x ZCE Rev. 2.1 BSDL Model

SPRM606.ZIP (8 KB) - BSDL 模型
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模擬型號

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS 模型
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模擬型號

AM335x ZCZ Rev. 2.0 BSDL Model (Rev. A)

SPRM549A.ZIP (8 KB) - BSDL 模型
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模擬型號

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL 模型
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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計算工具

POWEREST — 功率估計工具 (PET)

功耗估算工具 (PET) 讓使用者能深入瞭解特定 TI 處理器的功耗情況。本工具允許使用者選擇多種應用場景，不僅能掌握功耗數據，更能理解如何運用進階節能技術進一步降低整體功耗。

AM57x 與 AM437x 處理器專用 PET：

此可下載試算表提供使用者輸入應用所需裝置參數的機制。參數包含 IP 模組活動狀態/負載量、目標電源模式及電源管理使用情境。可設定多重運作條件並為每種狀態配置時間區段。電源估算數據已內嵌於試算表中，所有結果將直接在試算表內自動生成（無需上傳任何資料）。

AM57x 專用 PET：

(...)

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計算工具

SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF 工具試算表

Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。  

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參考設計

TIDEP0043 — Acontis EtherCAT 主站架構參考設計

Acontis EC-Master EtherCAT 主站堆疊是一款高度可攜的軟體堆疊，可用於各種嵌入式平台。EC-Master 支援高性能 TI Sitara MPU，並提供精密的 EtherCAT 主站解決方案，客戶可用來實作 EtherCAT 通訊介面電路板、EtherCAT 型 PLC 或動作控制應用。EC-Master 架構設計不需要安排其他任務，因此即使在無作業系統的平台上也可使用完整堆疊功能，例如在 AM335x 上支援的 TI Starterware。由於這種架構結合高速乙太網路驅動器，因此可在 Sitara 平台上以 100 微秒以內的短週期時間實作 EtherCAT (...)

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (GCZ) 324 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

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