BQ4802LY
- Real-Time Clock Counts Seconds Through Centuries in BCD Format
- bq4802Y: 5-V Operation
- bq4802LY: 3.3-V Operation
- On-Chip Battery-Backup Switchover Circuit With Nonvolatile Control for External SRAM
- Less Than 500 nA of Clock Operation Current in Backup Mode
- Microprocessor Reset With Push-Button Override
- Independent Watchdog Timer With Programmable Time-Out Period
- Power-Fail Interrupt Warning
- Programmable Clock Alarm Interrupt Active in Battery-Backup Mode
- Programmable Periodic Interrupt
- Battery-Low Warning
- 28-pin SOIC, TSSOP, and SNAPHAT Package Options
- APPLICATIONS
- Telecommunications Base Stations
- Servers
- Handheld Data Collection Equipment
- Medical Equipment
- Handheld Instrumentation
- Test Equipment
The bq4802Y/bq4802LY real-time clock is a low-power microprocessor peripheral that integrates a time-of-day clock, a century-based calendar, and a CPU supervisor, with package options including a 28-pin SOIC, TSSOP, or SNAPHAT that requires the bq48SH-28x6 to complete the two-piece module. The bq4802Y/ bq4802LY is ideal for fax machines, copiers, industrial control systems, point-of-sale terminals, data loggers, and computers.
The bq4802Y/bq4802LY provides direct connections for a 32.768-kHz quartz crystal and a 3-V backup battery. Through the use of the conditional chip enable output (CE\OUT) and battery voltage output (VOUT) pins, the bq4802Y/bq4802LY can write-protect and make non- volatile external SRAMs. The backup cell powers the real-time clock and maintains SRAM information the absence of system voltage. The crystal and battery are contained within the modules for a more integrated solution.
The bq4802Y/bq4802LY contains a temperature-compensated reference and comparator circuit that monitors the status of its voltage supply. When the bq4802Y/bq4802LY detects an out-of-tolerance condition, it generates an interrupt warning and subsequently a microprocessor reset. The reset stays active for 200 ms after VCC rises within tolerance, to allow for power supply and processor stabilization. The reset function also allows for an external push-button override.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Parallel Real-Time Clock with CPU Supervisor and External SRAM Non-Volatile datasheet (Rev. C) | 2002年 6月 3日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (DW) | 28 | Ultra Librarian |
| TSSOP (PW) | 28 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。