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非反相緩衝器和驅動器

CD74AC541

現行

具有 3 態輸出的 8 通道 1.5-V 至 5.5-V 緩衝器

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產品規格表

CD74AC541

現行
產品規格表 立即訂購

產品詳細資料

Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 160 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -55 to 125
Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 160 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SSOP (DB) 20 56.16 mm² 7.2 x 7.8
  • Buffered inputs
  • Typical propagation delay:
    4.5 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST®/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    -Fanout to 15 FAST® ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

FAST is a Registered Trademark of Fairchild Semiconductor Corp.
  • Buffered inputs
  • Typical propagation delay:
    4.5 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST®/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    -Fanout to 15 FAST® ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

FAST is a Registered Trademark of Fairchild Semiconductor Corp.

The CD54/74AC540, –541, and CD54/74ACT540, –541 octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT540 are inverting 3-state buffers having two active-LOW output enables. The CD54/74AC/ACT541 are non-inverting 3-state buffers having two active-LOW output enables.

The CD74AC540, –541, and CD74ACT540, –541 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Industrial (–40 to +85°C) and Extended Industrial/Military (–55 to +125°C).

The CD54AC540, –541, and CD54ACT540, –541, available in chip form (H suffix), are operable over the –55 to +125°C temperature range.

The CD54/74AC540, –541, and CD54/74ACT540, –541 octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT540 are inverting 3-state buffers having two active-LOW output enables. The CD54/74AC/ACT541 are non-inverting 3-state buffers having two active-LOW output enables.

The CD74AC540, –541, and CD74ACT540, –541 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Industrial (–40 to +85°C) and Extended Industrial/Military (–55 to +125°C).

The CD54AC540, –541, and CD54ACT540, –541, available in chip form (H suffix), are operable over the –55 to +125°C temperature range.
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類型 標題 日期
* Data sheet Octal Buffer/Line Drivers, 3-State datasheet (Rev. A) 1999年 11月 16日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
More literature HiRel Unitrode Power Management Brochure 2009年 7月 7日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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使用指南: PDF | HTML
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模擬型號

CD74AC541 Behavioral SPICE Model

SCHM045.ZIP (7 KB) - PSpice Model
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模擬型號

CD74AC541 IBIS Model

SCHM003.ZIP (27 KB) - IBIS Model
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封裝 引腳 下載
PDIP (N) 20 檢視選項
SOIC (DW) 20 檢視選項
SSOP (DB) 20 檢視選項
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