CDCBT1001
- Low additive jitter and phase noise:
- 0.8ps maximum 12kHz to 5MHz additive RMS jitter (fout = 24MHz)
- –120dBc/Hz maximum phase noise at 1kHz offset (fout = 24MHz)
- –148dBc/Hz maximum phase noise floor (fout = 24MHz, foffset ≥ 1MHz)
- 5ns 20% to 80% rise/fall time
- 10ns propagation delay
- Low current consumption
- –40°C to 85°C operating temperature range
- Flexible output from operational frequency
The CDCBT1001 is a 1.2V to 3.3V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%. VDD_OUT = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%.
The 12kHz to 5MHz additive RMS jitter at 24MHz is less than 0.8ps.
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCBT1001 1.2V to 3.3 V Clock Buffer and Level Translator datasheet (Rev. A) | PDF | HTML | 2025/10/24 | ||
| 證書 | CDCBT1001EVM EU RoHS Declaration of Conformity (DoC) | 2022/3/25 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| X2SON (DPW) | 5 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。