產品詳細資料

Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (max) (MHz) 800 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features I2C, Pin programmable, SPI Rating Catalog
Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (max) (MHz) 800 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features I2C, Pin programmable, SPI Rating Catalog
VQFN (RGZ) 48 49 mm² 7 x 7
  • Superior Performance with Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical
      Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
      Typical Jitter)
    • 0.5 W Typical Power Consumption
    • High Channel-to-Channel Isolation and
      Excellent PSRR
    • Device Performance Customizable Through
      Flexible 1.8 V, 2.5 V and 3.3 V Power
      Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-divided Differential Clock
      Outputs Supporting LVPECL-like, CML, or
      LVDS-like Signaling
    • 4x Fractional or Integer Divided Differential
      Clock Outputs Supporting HCSL, LVDS-like
      Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1
      ppm Frequency Error and Eliminates need for
      Crystal Oscillators and Other Clock Generators
    • Output frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for
    Smart Switching
  • SPI, I2C™, and Pin Programmable
  • Professional user GUI for Quick Design
    Turnaround
  • 7 × 7 mm 48-QFN package (RGZ)
  • –40 °C to 85 °C temperature range
  • Superior Performance with Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical
      Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
      Typical Jitter)
    • 0.5 W Typical Power Consumption
    • High Channel-to-Channel Isolation and
      Excellent PSRR
    • Device Performance Customizable Through
      Flexible 1.8 V, 2.5 V and 3.3 V Power
      Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-divided Differential Clock
      Outputs Supporting LVPECL-like, CML, or
      LVDS-like Signaling
    • 4x Fractional or Integer Divided Differential
      Clock Outputs Supporting HCSL, LVDS-like
      Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1
      ppm Frequency Error and Eliminates need for
      Crystal Oscillators and Other Clock Generators
    • Output frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for
    Smart Switching
  • SPI, I2C™, and Pin Programmable
  • Professional user GUI for Quick Design
    Turnaround
  • 7 × 7 mm 48-QFN package (RGZ)
  • –40 °C to 85 °C temperature range

The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm × 7 mm QFN package.

The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm × 7 mm QFN package.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 2
類型 標題 日期
* Data sheet CDCM6208V1F 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers datasheet PDF | HTML 2015年 5月 7日
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024年 4月 30日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGZ) 48 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片