DAC3151
- Single Channel
- Resolution
- DAC3151: 10-Bit
- DAC3161: 12-Bit
- DAC3171: 14-Bit
- Maximum Sample Rate: 500 MSPS
- Pin-Compatible Family
- Input Interface:
- Parallel LVDS Inputs
- Single or Dual DDR Data Clock
- Internal FIFO
- Chip to Chip Synchronization
- Power Dissipation: 375 mW
- Spectral Performance at 20 MHz IF
- SNR:
- DAC3151: 62 dBFS
- DAC3161: 72 dBFS
- DAC3171: 76 dBFS
- SFDR:
- DAC3151: 76 dBc
- DAC3161: 77 dBc
- DAC3171: 78 dBc
- SNR:
- Current Sourcing DACs
- Compliance Range: –0.5 V to +1 V
- Package: 64-pin VQFN (9 mm × 9 mm)
The DAC3151, DAC3161, and DAC3171 (DAC31x1) are a family of single-channel, 500-MSPS digital-to-analog converters (DACs). This family uses a 10-,
12-, or 14-bit wide LVDS digital bus with an input FIFO. The 14-bit DAC3171 also supports a DDR 7-bit LVDS interface mode. FIFO input and output pointers can be synchronized across multiple devices for precise signal synchronization. The DAC outputs are current sourcing, and terminate to GND with a compliance range of –0.5 V to +1 V. The DAC31x1 are pin compatible with the DAC31x4, dual-channel, 10-, 12-, and 14-bit, 500-MSPS digital-to-analog converters.
The DAC31x1 are available in a VQFN-64 package that is specified over the full industrial temperature range (–40°C to +85°C).
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DAC31x1 Single-Channel, 14-,12-, and 10-Bit, 500-MSPS, Digital-to-Analog Converters datasheet (Rev. D) | PDF | HTML | 2018年 2月 16日 |
| More literature | TI and Altera Ease Design Process with Compatible Evaluation Tools | 2011年 4月 25日 | ||
| More literature | TI and Xilinx Ease Design Process with Compatible Evaluation Tools | 2011年 4月 25日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。