DMVA3
- High-Performance DaVinci Digital Media Processors
- Up to 970-MHz ARM® Cortex™-A8 RISC Processor
- Up to 1940 ARM Cortex-A8 MIPS
- ARM Cortex-A8 Core
- ARMv7 Architecture
- In-Order, Dual-Issue, Superscalar Processor Core
- NEON™ Multimedia Architecture
- Supports Integer and Floating Point
- Jazelle® RCT Execution Environment
- ARMv7 Architecture
- ARM Cortex-A8 Memory Architecture
- 32KB of Instruction and Data Caches
- 256KB of L2 Cache with ECC
- 64KB of RAM, 48KB of Boot ROM
- 256KB of On-Chip Memory Controller (OCMC) RAM
- Imaging Subsystem (ISS)
- Camera Sensor Connection
- Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
- CSI2 Serial Connection
- Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
- Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
- Image Pipe (IPIPE) for Real-Time Image and Video Processing
- Resizer
- Resizing Image and Video From 1/16x to 8x
- Generating Two Different Resizing Outputs Concurrently
- Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
- Camera Sensor Connection
- Vision Coprocessor
- Face Detect (FD) Engine
- Hardware Face Detection for up to 35 Faces Per Frame
- Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
- Encode, Decode, Transcode Operations
- H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
- Fourth-Generation Motion-Compensated Noise Filter
- Media Controller
- Controls the HDVPSS, HDVICP2, Vision Coprocessor, and ISS
- Endianness
- ARM Instructions and Data – Little Endian
- HD Video Processing Subsystem (HDVPSS)
- Two 165-MHz HD Video Capture Inputs
- One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
- One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
- Two 165-MHz HD Video Display Outputs
- One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
- Component HD Analog Output
- Composite Analog Output
- Digital HDMI 1.3 Transmitter with Integrated PHY
- Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
- Three Graphics Layers and Compositors
- Two 165-MHz HD Video Capture Inputs
- 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
- Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
- Up to Two x 16 Devices, 2GB of Total Address Space
- Dynamic Memory Manager (DMM)
- Programmable Multi-Zone Memory Mapping
- Enables Efficient 2D Block Accesses
- Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
- General-Purpose Memory Controller (GPMC)
- 8- or 16-Bit Multiplexed Address and Data Bus
- 512MB of Total Address Space Divided Among up to 8 Chip Selects
- Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
- Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
- Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
- Enhanced Direct Memory Access (EDMA) Controller
- Four Transfer Controllers
- 64 Independent DMA Channels
- 8 QDMA Channels
- Ethernet Switch with Dual 10-, 100-, or
1000-Mbps External Interfaces (EMAC Software)- IEEE 802.3 Compliant (3.3-V I/O Only)
- MII/RMII/GMII/RGMII Media Independent Interfaces
- Management Data I/O (MDIO) Module
- Reset Isolation
- IEEE 1588 Time-Stamping and Industrial Ethernet Protocols
- Dual USB 2.0 Ports with Integrated PHYs
- USB2.0 High- and Full-Speed Clients
- USB2.0 High-, Full-, and Low-Speed Hosts
- Supports End Points 0-15
- One PCI Express 2.0 Port with Integrated PHY
- Single Port with 1 Lane at 5.0 GT/s
- Configurable as Root Complex or Endpoint
- Eight 32-Bit General-Purpose Timers (Timer1–8)
- One System Watchdog Timer (WDT0)
- Three Configurable UART/IrDA/CIR Modules
- UART0 with Modem Control Signals
- Supports up to 3.6864 Mbps
- SIR, MIR, FIR (4.0 MBAUD), and CIR
- Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
- Each with Four Chip Selects
- Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
- Supporting up to 1-, 4-, or 8-Bit Modes
- Dual Controller Area Network (DCAN) Module
- CAN Version 2 Part A, B
- Four Inter-Integrated Circuit (I2C Bus™) Ports
- Two Multichannel Audio Serial Ports (McASP)
- Six Serializer Transmit and Receive Ports
- Two Serializer Transmit and Receive Ports
- DIT-Capable For S/PDIF (All Ports)
- Four Audio Tracking Logic (ATL) Modules
- One Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHY
- Direct Interface to 1 Hard Disk Drive
- Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
- Real-Time Clock (RTC)
- One-Time or Periodic Interrupt Generation
- Up to 125 General-Purpose I/O (GPIO) Pins
- One Spin Lock Module with up to 128 Hardware Semaphores
- One Mailbox Module with 12 Mailboxes
- On-Chip ARM ROM Bootloader (RBL)
- Power, Reset, and Clock Management
- SmartReflex™ Technology (Level 2b)
- Multiple Independent Core Power Domains
- Multiple Independent Core Voltage Domains
- Support for Two Operating Points (OPP120 and OPP100) per Voltage Domain
- Clock Enable and Disable Control for Subsystems and Peripherals
- 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
- IEEE 1149.1 (JTAG) Compatible
- 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
- 45-nm CMOS Technology
- 1.8- and 3.3-V Dual Voltage Buffers for General I/O
All trademarks are the property of their respective owners.
DMVA3 and DMVA4 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of multichannel Digital Video Recorders (DVR), Network Video Recorders (NVR), HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD and HD resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 or more than 8 channels of D1 real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DMVA3/4 are uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.
The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. In addition, the devices include a custom vision coprocessor with an available suite of TI-developed video analytics functions. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); a vision coprocessor; up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; two Controller Area Network (DCAN) modules; one Serial ATA (SATA) 3.0 Gbps controller with integrated PHY; a Spin Lock; and Mailbox.
Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.
透過第三方支援
此產品沒有 TI 的持續直接設計支援。如在進行設計時需相關支援，您可聯絡以下第三方：D3 Engineering、elnfochips、Ittiam Systems、Path Partner Technology 或 Z3 Technologies。
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DMVA3 and DMVA4 DaVinci Digital Media Processor datasheet (Rev. B) | 2013年 12月 18日 | |
| * | Errata | DMVA3 and DMVA4 DaVinci Digital Media Processor SE (Silicon Rev. 1.1, 1.0) (Rev. A) | 2013年 12月 18日 |
設計與開發
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TMDSEMU200-U — XDS200 USB 偵錯探測器
XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。
XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)
TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器
XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。
所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。
XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)
TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器
The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)
PROCESSORS-3P-SEARCH — Arm 架構 MPU、arm 架構 MCU 和 DSP 第三方搜尋工具
搜尋工具會依產品類型分類，如下所示：
- 工具包括 IDE/編譯器、偵錯和追蹤、模擬和建模軟體及快閃程式設計師。
- OS 包含 TI 處理器支援的作業系統。
- 應用軟體意指特定應用程式軟體，包括在 TI 處理器上執行的中介軟體和程式庫。
- SOM 意指系統模組解決方案
| 封裝 | 引腳 | 下載 |
|---|---|---|
| FCCSP (AAR) | 609 | 檢視選項 |
訂購與品質
- RoHS
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- MSL 等級/回焊峰值
- MTBF/FIT 估算值
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- 進行中可靠性監測
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