DRV612
- DirectPath™
- Eliminates Pops and Clicks
- Eliminates Output DC-Blocking Capacitors
- 3-V to 3.6-V Supply Voltage
- Low Noise and THD
- SNR > 105 dB at –1× Gain
- Vn < 12 µVms, 20 Hz to 20 kHz at –1× Gain (Typical)
- THD+N < 0.003% at 10-kΩ Load and –1× Gain
- 2-Vrms Output Voltage Into 600-Ω Load
- Single-Ended Input and Output
- Programmable Gain Select Reduces Component Count
- 13× Gain Values
- Active Mute With More Than 80-dB Attenuation
- Short-Circuit and Thermal Protection
- ±8-kV HBM ESD-Protected Outputs
The DRV612 is a single-ended, 2-Vrms stereo line driver designed to reduce component count, board space, and cost. It is ideal for single-supply electronics where size and cost are critical design parameters.
The DRV612 does not require a power supply greater than 3.3 V to generate its 5.6-VPP output, nor does it require a split-rail power supply.
The DRV612 device is designed using TI’s patented DirectPath technology, which integrates a charge pump to generate a negative supply rail that provides a clean, pop-free ground-biased output. The DRV612 is capable of driving 2 Vms into a 600-Ω load. DirectPath technology also allows the removal of the costly output dc-blocking capacitors.
The device has fixed-gain single-ended inputs with a gain-select pin. Using a single resistor on this pin, the designer can choose from 13 internal programmable gain settings to match the line driver with the codec output level. The device also reduces the component count and board space.
Line outputs have ±8-kV HBM ESD protection, enabling a simple ESD protection circuit. The DRV612 has built-in active mute control with more that 80-dB attenuation for pop-free mute on/off control.
The DRV612 is available in a 14-pin TSSOP and 16-pin VQFN. For a footprint-compatible stereo headphone driver, see the TPA6139A2.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DRV612 2-Vrms DirectPath Line Driver With Programmable-Fixed Gain datasheet (Rev. C) | PDF | HTML | 2016年 7月 28日 |
| Application note | DAC Post-Filter Design Based on DRV6xx Family (Rev. A) | 2010年 11月 23日 | ||
| EVM User's guide | DRV612 EVM User's Guide | 2010年 11月 10日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 14 | Ultra Librarian |
| VQFN (RGT) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。