DS90C385A
- Pin-to-Pin Compatible to DS90C383, DS90C383A and DS90C385
- No Special Start-Up Sequence Required between Clock/Data and /PD Pins. Input Signals (Clock and Data) can be Applied Either Before or After the Device is Powered.
- Support Spread Spectrum Clocking up to 100kHz Frequency Modulation and Deviations of ±2.5% Center Spread or -5% Down Spread
- “Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low When Input Clock is Missing and When /PD Pin is Logic High
- 18 to 87.5 MHz Shift Clock Support
- Tx Power Consumption < 147 mW (typ) at 87.5MHz Grayscale
- Tx Power-Down Mode < 60 μW (typ)
- Supports VGA, SVGA, XGA, SXGA(Dual Pixel), SXGA+(Dual Pixel), UXGA(Dual Pixel).
- Narrow Bus Reduces Cable Size and Cost
- Up to 2.45 Gbps Throughput
- Up to 306.25Megabyte/sec Bandwidth
- 345 mV (typ) Swing LVDS Devices for Low EMI
- PLL Requires No External Components
- Compliant to TIA/EIA-644 LVDS standard
- Low Profile 56-lead TSSOP Package
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The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90C383A and DS90C385. The DS90C385A has additional features and improvements making it an ideal replacement for DS90C383, DS90C383A and DS90C385. family of LVDS Transmitters.
The DS90C385A transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 306.25Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spread Spectrum Clocking support.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90C385A 3.3V Prog LVDS Trans 24-Bit FPD Link-87.5 MHz datasheet (Rev. K) | 2013/4/17 | |||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 應用說明 | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018/6/29 | ||||
| 應用說明 | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017/8/8 | ||||
| 使用指南 | FLINK3V8BT-85 Evaluation Kit (Rev. A) | 2016/8/24 | ||||
| 應用說明 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016/1/13 | |||
| 應用說明 | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004/5/15 | ||||
| 應用說明 | AN-1056 STN Application Using FPD-Link | 2004/5/14 | ||||
| 應用說明 | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004/5/14 |
設計與開發
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FLINK3V8BT-85 — 適用於 FPD-Link 系列之串聯器和解串器 LVDS 產品的評估套件
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
TIDA-010013 — 用於 Sitara™ 處理器的 RGB 至 OLDI/LVDS 顯示橋接器參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
訂購與品質
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