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時鐘與計時
時鐘抖動清除器

LMK04610

現行

具有雙 PLL 的超低雜訊、低功耗且符合 JESD204B 標準的時鐘抖動清除器

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產品規格表

LMK04610

現行
產品規格表 立即訂購

產品詳細資料

Number of input channels 2 Number of outputs 10 RMS jitter (fs) 65 Features JESD204B Output frequency (min) (MHz) 0.03 Output frequency (max) (MHz) 2000 Output type LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
Number of input channels 2 Number of outputs 10 RMS jitter (fs) 65 Features JESD204B Output frequency (min) (MHz) 0.03 Output frequency (max) (MHz) 2000 Output type LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
VQFN (RTQ) 56 64 mm² (8 mm × 8 mm)
  • Dual-loop PLL architecture
  • Ultra low noise (10 kHz to 20 MHz):
    • 48-fs RMS jitter at 1966.08 MHz
    • 50-fs RMS jitter at 983.04 MHz
    • 61-fs RMS jitter at 122.88 MHz
  • –165-dBc/Hz noise floor at 122.88 MHz
  • JESD204B support
    • Single shot, pulsed, and continuous SYSREF
  • 10 differential output clocks in 8 frequency groups
    • Programmable output swing between 700 mVpp to 1600 mVpp
    • Each output pair can be configured to SYSREF clock output
    • 16-bit channel divider
    • Minimum SYSREF frequency of 25 kHz
    • Maximum output frequency of 2 GHz
    • Precision digital delay, dynamically adjustable
      • Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
    • 60-ps step analog delay
    • 50% duty cycle output divides, 1 to 65535
      (even and odd)
  • Two reference inputs
    • Holdover mode, when inputs are lost
    • Automatic and manual switch-over modes
    • Loss-of-signal (LOS) detection
  • 0.88-W typical power consumption with 10 outputs active
  • Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
  • Fully integrated programmable loop filter
  • PLL2
    • PLL2 phase detector rate up to 250 MHz
    • OSCin frequency-doubler
    • Integrated low-noise VCO
  • Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
  • 3- or 4-wire SPI interface (4-wire is default)
  • –40ºC to +85ºC industrial ambient temperature
  • Supports 105ºC PCB temperature (measured at thermal pad)
  • LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitch
  • Dual-loop PLL architecture
  • Ultra low noise (10 kHz to 20 MHz):
    • 48-fs RMS jitter at 1966.08 MHz
    • 50-fs RMS jitter at 983.04 MHz
    • 61-fs RMS jitter at 122.88 MHz
  • –165-dBc/Hz noise floor at 122.88 MHz
  • JESD204B support
    • Single shot, pulsed, and continuous SYSREF
  • 10 differential output clocks in 8 frequency groups
    • Programmable output swing between 700 mVpp to 1600 mVpp
    • Each output pair can be configured to SYSREF clock output
    • 16-bit channel divider
    • Minimum SYSREF frequency of 25 kHz
    • Maximum output frequency of 2 GHz
    • Precision digital delay, dynamically adjustable
      • Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
    • 60-ps step analog delay
    • 50% duty cycle output divides, 1 to 65535
      (even and odd)
  • Two reference inputs
    • Holdover mode, when inputs are lost
    • Automatic and manual switch-over modes
    • Loss-of-signal (LOS) detection
  • 0.88-W typical power consumption with 10 outputs active
  • Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
  • Fully integrated programmable loop filter
  • PLL2
    • PLL2 phase detector rate up to 250 MHz
    • OSCin frequency-doubler
    • Integrated low-noise VCO
  • Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
  • 3- or 4-wire SPI interface (4-wire is default)
  • –40ºC to +85ºC industrial ambient temperature
  • Supports 105ºC PCB temperature (measured at thermal pad)
  • LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitch

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. B) PDF | HTML 2018/1/9
應用說明 JESD204B Multi-Device Synchronization Using LMK0461x PDF | HTML 2017/8/16
應用說明 LMK0461x Phase Noise Performance With DC-DC Converters (Rev. B) 2017/7/20
應用說明 SDPLL for LMK046xx Family 2017/5/15

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開發板

LMK04610EVM — 具有雙 PLL 且符合 JESD204B 標準的 LMK04610 超低雜訊和低功耗時鐘抖動清除器 EVM

LMK04610EVM 配備 LMK04610 超低雜訊、低功耗且符合 JESD204B 規範的雙迴路抖動清除器。當所有輸出運作時功耗僅為 900mW，LMK04610 可搭配低雜訊 VCXO 模組支援低於 74fs 抖動（頻率範圍為 12kHz 至 20MHz）。內建 LDO 提供高 PSRR，可支援 DC/DC 轉換器。
使用指南: PDF
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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。

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模擬型號

LMK0461X IBIS Model

SNAM204.ZIP (126 KB) - IBIS 模型
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CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

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