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LMK5C33414A

現行

具有 JESD204B/C 和 BAW VCO 的三 DPLL、三 APLL、四輸入和 14 輸出網路同步器

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產品規格表

LMK5C33414A

現行
產品規格表 立即訂購

產品詳細資料

Function Clock network synchronizer Number of outputs 14 RMS jitter (fs) 47 Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 1250 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Output type CML, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features JESD204B Rating Catalog Operating temperature range (°C) -40 to 105 Number of input channels 4
Function Clock network synchronizer Number of outputs 14 RMS jitter (fs) 47 Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 1250 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Output type CML, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features JESD204B Rating Catalog Operating temperature range (°C) -40 to 105 Number of input channels 4
VQFN (RGC) 64 81 mm² 9 x 9
  • Ultra-low jitter BAW VCO based Wireless clocks
    • 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz
    • 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz

  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop bandwidth from 1 mHz to 4 kHz
    • < 1-ppt DCO frequency adjustment step size
  • Four differential or single-ended DPLL inputs
    • 1-Hz (1-PPS) to 800-MHz input frequency
    • Digital holdover and hitless switching
  • 14 differential outputs with programmable HSDS/LVPECL, LVDS and HSCL output formats
    • Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 12 differential outputs
    • 1-Hz (1-PPS) to 1250-MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I 2C, 3-wire SPI, or 4-wire SPI interface
  • Ambient operating temperature: –40°C to 85°C
  • Ultra-low jitter BAW VCO based Wireless clocks
    • 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz
    • 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz

  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop bandwidth from 1 mHz to 4 kHz
    • < 1-ppt DCO frequency adjustment step size
  • Four differential or single-ended DPLL inputs
    • 1-Hz (1-PPS) to 800-MHz input frequency
    • Digital holdover and hitless switching
  • 14 differential outputs with programmable HSDS/LVPECL, LVDS and HSCL output formats
    • Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 12 differential outputs
    • 1-Hz (1-PPS) to 1250-MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I 2C, 3-wire SPI, or 4-wire SPI interface
  • Ambient operating temperature: –40°C to 85°C

The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.

APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology and can generate 491.52-MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation may be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I 2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.

APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology and can generate 491.52-MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation may be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I 2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
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類型 標題 日期
* Data sheet LMK5C33414ANetwork SynchronizerWith JED204B/JED204C and BAW VCO for Wireless Communications datasheet PDF | HTML 2023年 12月 6日
EVM User's guide LMK5C33414A Evaluation Module User's Guide PDF | HTML 2023年 12月 21日

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LMK5C33414AEVM — LMK5C33414A 評估模組

LMK5C33414A 評估模組 (EVM) 是 LMK5C33414A 網路時鐘產生器和同步器。EVM 可用於裝置評估、合規測試和系統原型設計。  LMK5C33414A 整合了三個類比 PLL (APLL)、三個數位 PLL (DPLL) 與可編程迴路頻寬。EVM 包括 SMA 連接器，用於時鐘輸入、振盪器輸入和時鐘輸出，以便與 50Ω 測試設備介接。板載 TCXO 可用來對 LMK5C33414A 操作時的自由運轉、鎖定或維持模式進行評估。EVM 可透過板載 USB 微控制器 (MCU) 介面，使用配備 TICS Pro 軟體圖形使用者介面 (GUI) 的 PC 進行配置。TICS (...)

使用指南: PDF | HTML
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LMK5B33216 Family IBIS model

SNAM295.ZIP (239 KB) - IBIS Model
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CLOCK-PERFDATA-DESIGN — Clock performance data and register settings for clock generators, network synchronizers, jitter cleaners, and other clocking devices.

Configuration, raw phase noise data, noise plots, and register data for common use cases on clock generators, network synchronizers, jitter cleaners, and other clocking devices
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時脈網路同步器
LMK5B33216 — 具有整合式 2.5-GHz 突破性體聲波 VCO 的 16 輸出、三 DPLL 和 APLL 網路同步器 LMK5B33414 — 具有整合式 2.5-GHz 突破性體聲波 VCO 的 14 輸出、三 DPLL 和 APLL 網路同步器 LMK5C33414AS1 — 具有 BAW VCO IEEE-1588 支援的三 DPLL、三 APLL、四輸入、14 輸出網路同步器 LMK5C33414A — 具有 JESD204B/C 和 BAW VCO 的三 DPLL、三 APLL、四輸入和 14 輸出網路同步器 LMK5C33216A — 具有 JESD204B/C 和 BAW VCO 的三 DPLL、三 APLL、雙輸入和 16 輸出網路同步器 LMK5C33216AS1 — 具有 BAW VCO IEEE-1588 支援的三 DPLL、三 APLL、雙輸入、16 輸出網路同步器 LMK5C22212A — 具有 BAW VCO 的三 DPLL、雙 APLL、雙輸入和 12 輸出網路同步器  LMK5C22212AS1 — 具有 BAW VCO 和 IEEE-1588 支援的三 DPLL、雙 APLL、雙輸入、12 輸出網路同步器
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TICSPRO-SW — 德州儀器 (TI) 時鐘和合成器 (TICS) Pro 軟體
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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