產品詳細資料

Bits (#) 2 Data rate (max) (Mbps) 200 Topology Open drain, Push-Pull Vin (min) (V) 0.95 Vin (max) (V) 3.6 Vout (min) (V) 1.8 Vout (max) (V) 5.5 Applications GPIO, I2C, MDIO, PMBus, SMBus Features Single supply Prop delay (ns) 1.3 Technology family LSF Supply current (max) (mA) 0.0125 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 2 Data rate (max) (Mbps) 200 Topology Open drain, Push-Pull Vin (min) (V) 0.95 Vin (max) (V) 3.6 Vout (min) (V) 1.8 Vout (max) (V) 5.5 Applications GPIO, I2C, MDIO, PMBus, SMBus Features Single supply Prop delay (ns) 1.3 Technology family LSF Supply current (max) (mA) 0.0125 Rating Catalog Operating temperature range (°C) -40 to 125
X2SON (DTQ) 6 0.8 mm² 1 x 0.8
  • Provide bidirectional voltage translation with no direction pin needed (VEXTA needs to be 0.8V less than VEXTB for best signal integrity)
  • Supports switch configuration implementation when VEXTA = VEXTB
  • Supports up to 100MHz up translation and greater than 100MHz down translation at≤ 30pF capacitive load and up To 40MHz up or down translation at 50pF capacitive load
  • Allows bidirectional voltage-level translation between
    • 0.95V ↔ 1.8/2.5/3.3/5V
    • 1.2V ↔ 1.8/2.5/3.3/5V
    • 1.8V ↔ 2.5/3.3/5V
    • 2.5V ↔ 3.3/5V
    • 3.3V ↔ 5V
  • Low standby current
  • 5V tolerance I/O port to support TTL
  • Low RON provides less signal distortion
  • High-impedance I/O pins for EN = Low
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance >100mA per JESD 17
  • –40°C to 125°C operating temperature range
  • Provide bidirectional voltage translation with no direction pin needed (VEXTA needs to be 0.8V less than VEXTB for best signal integrity)
  • Supports switch configuration implementation when VEXTA = VEXTB
  • Supports up to 100MHz up translation and greater than 100MHz down translation at≤ 30pF capacitive load and up To 40MHz up or down translation at 50pF capacitive load
  • Allows bidirectional voltage-level translation between
    • 0.95V ↔ 1.8/2.5/3.3/5V
    • 1.2V ↔ 1.8/2.5/3.3/5V
    • 1.8V ↔ 2.5/3.3/5V
    • 2.5V ↔ 3.3/5V
    • 3.3V ↔ 5V
  • Low standby current
  • 5V tolerance I/O port to support TTL
  • Low RON provides less signal distortion
  • High-impedance I/O pins for EN = Low
  • Flow-through pinout for easy PCB trace routing
  • Latch-up performance >100mA per JESD 17
  • –40°C to 125°C operating temperature range

The LSF0002 supports bidirectional voltage translation without the need for DIR pin, which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up to 40MHz up or down translation at 50pF capacitive load, which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port, which makes it compatible with TTL levels in industrial and telecom applications. The LSF family can set up different voltage translation levels, which makes it very flexible.

Unlike the LSF0x0x family, the LSF0002 does not require VREF_A and VREF_B power supplies and the 200kΩ bias resistor. The LSF0002 utilizes the VBIAS pin that enables translation by being biased to the same voltage as the lower power supply at the I/Os that is being translated to and from.

The LSF0002 supports bidirectional voltage translation without the need for DIR pin, which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up to 40MHz up or down translation at 50pF capacitive load, which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port, which makes it compatible with TTL levels in industrial and telecom applications. The LSF family can set up different voltage translation levels, which makes it very flexible.

Unlike the LSF0x0x family, the LSF0002 does not require VREF_A and VREF_B power supplies and the 200kΩ bias resistor. The LSF0002 utilizes the VBIAS pin that enables translation by being biased to the same voltage as the lower power supply at the I/Os that is being translated to and from.

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* Data sheet LSF0002 Ultra-Small Auto-Bidirectional Translator for Open Drain or Push Pull Applications datasheet (Rev. A) PDF | HTML 2025年 9月 8日
Application note Designing and Manufacturing with TI's X2SON Packages 2017年 8月 23日

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模擬型號

LSF0002 IBIS Model

SDLM076.ZIP (56 KB) - IBIS Model
參考設計

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Design guide: PDF
電路圖: PDF
參考設計

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物聯網 (IoT) 革命可有效連接應用與儀器,實現電池供電的廣泛超低功耗感測器部署。  TI 進階感測器和低功耗連線裝置等新技術使這些儀器能夠設計成電池供電無線系統,大幅改善成本、部署、可靠性、性能和複雜性。

TIDA-01014 參考設計採用德州儀器的 SimpleLink™ 超低功耗無線微控制器 (MCU) 平台,運用 TIDA-01012 無線 DMM 參考設計,展示 bq27426 如何用來強化電池管理系統的電量計性能,最終達到最佳耗電量。TIDA-01014 具備無線連接、4½ 位數、100kHz 真 RMS DMM,支援 Bluetooth 低功耗® (BLE) 無線連線、NFC (...)

Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
X2SON (DTQ) 6 Ultra Librarian

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  • 認證摘要
  • 進行中持續性的可靠性監測
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