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音訊 DAC

PCM5100A-Q1

現行

具有 32 位元、384kHz PCM 介面的汽車類 2VRMS DirectPath™、100dB 音訊立體聲道 DAC

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產品規格表

現在提供此產品的更新版本

open-in-new 比較替代產品
功能相同，但引腳輸出與所比較的裝置不同
最新 TAD5112-Q1 現行 具有 110dB 動態範圍及耳機與線路驅動器的車用低功耗立體聲道音訊 DAC Smaller package, higher SNR performance, and more programmability

PCM5100A-Q1

現行
產品規格表 立即訂購

產品詳細資料

Number of DAC channels 2 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (Bits) 32 DAC SNR (typ) (dB) 100 Analog outputs 2 Architecture Delta Sigma with line driver Operating temperature range (°C) -40 to 125 Rating Automotive
Number of DAC channels 2 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (Bits) 32 DAC SNR (typ) (dB) 100 Analog outputs 2 Architecture Delta Sigma with line driver Operating temperature range (°C) -40 to 125 Rating Automotive
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).
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PCM5101A-Q1 現行 具有 32 位元、384kHz PCM 介面的汽車類 2VRMS DirectPath™、106dB 音訊立體聲道 DAC Higher SNR performance
引腳對引腳且具備與所比較裝置相同的功能
PCM5100A 現行 具 32 位元、384kHz PCM 介面的 2VRMS DirectPath™;、100dB 音訊立體聲道 DAC Catalog version without AEC-Q100 qualification

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類型 標題 日期
* Data sheet PCM510xA 2.1 VRMS, 112/106/100 dB Audio Stereo DAC with PLL and 32-bit, 384 kHz PCM Interface datasheet (Rev. C) PDF | HTML 2015年 5月 6日
EVM User's guide PCM510xEVM-U User Guide (Rev. C) 2014年 10月 13日
Application note A Low Noise, Low Distortion Design for Antialiasing and Anti-Imaging Filters 2000年 9月 27日

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開發板

PCM5102EVM-U — PCM5102 評估模組

PCM5102EVM-U 是一款完整的評估套件，可與執行 Microsoft Windows™ 作業系統的個人電腦搭配使用。所需的評估軟體可透過網路前往 PCM5102 產品資料夾取得。

PCM5102EVM 採用德州儀器 (TI) EVM 外型尺寸，可直接評估裝置性能和運作特性，並簡化軟體開發和系統原型設計。

PCM5102EVM-U 只需一條連接至 PC 的 mini-USB 纜線即可運作。透過 USB 連接，就能為 EVM 供電、控制及串流音訊資料至 EVM，減少設定與配置作業。EVM 還可由外部控制訊號和音訊資料來進階操作，以便進行原型設計並連接至其他開發或系統。

 

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