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產品詳細資料

Number of DAC channels 2 Sampling rate (max) (kHz) 384 Control interface H/W, I2C, SPI Resolution (Bits) 32 DAC SNR (typ) (dB) 114 Analog outputs 2 Architecture Delta Sigma with Line Driver Operating temperature range (°C) -25 to 85 Rating Catalog
Number of DAC channels 2 Sampling rate (max) (kHz) 384 Control interface H/W, I2C, SPI Resolution (Bits) 32 DAC SNR (typ) (dB) 114 Analog outputs 2 Architecture Delta Sigma with Line Driver Operating temperature range (°C) -25 to 85 Rating Catalog
VQFN (RHB) 32 25 mm² 5 x 5
  • Differential DirectPath™ Ground Biased Outputs
  • Smart Amplifier Technology
  • Market-Leading Low Out-of-Band Noise
  • Selectable Digital-Filter Latency and Performance
  • No DC Blocking Capacitors Required
  • Integrated Negative Charge Pump
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute for 120dB Mute SNR
  • Integrated High-Performance Audio PLL With BCK
    Reference to Generate SCK Internally
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • SPI or I2C Control
  • Hardware Configuration
  • Automatic Power-Save Mode When LRCK And BCK
    Are Deactivated
  • 1.8V or 3.3V Failsafe LVCMOS Digital Inputs
  • Single Supply Operation:
    • 3.3V Analog, 1.8V or 3.3V Digital
  • Integrated Power-On Reset
  • Small 32-pin VQFN Package
  • Differential DirectPath™ Ground Biased Outputs
  • Smart Amplifier Technology
  • Market-Leading Low Out-of-Band Noise
  • Selectable Digital-Filter Latency and Performance
  • No DC Blocking Capacitors Required
  • Integrated Negative Charge Pump
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute for 120dB Mute SNR
  • Integrated High-Performance Audio PLL With BCK
    Reference to Generate SCK Internally
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • SPI or I2C Control
  • Hardware Configuration
  • Automatic Power-Save Mode When LRCK And BCK
    Are Deactivated
  • 1.8V or 3.3V Failsafe LVCMOS Digital Inputs
  • Single Supply Operation:
    • 3.3V Analog, 1.8V or 3.3V Digital
  • Integrated Power-On Reset
  • Small 32-pin VQFN Package

The PCM5252 is a monolithic CMOS integrated circuit that includes a stereo digital-to-analog converter and additional support circuitry in a small QFN package. The PCM5252 uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

The PCM5252 integrates a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators and other differentiating features to their products.

The PCM5252 integrates ROM components of TI’s PurePath™ Smart Amp technology, which allows speakers to be driven with more peak power than their average-power rating, without damage to the speaker by voice coil over excursion or thermal overload.

The PCM5252 provides 4.2VRMS ground-centered differential outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single supply line drivers.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Block diagrams for the can be found at Functional Block Diagram.

The PCM5252 is a monolithic CMOS integrated circuit that includes a stereo digital-to-analog converter and additional support circuitry in a small QFN package. The PCM5252 uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

The PCM5252 integrates a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators and other differentiating features to their products.

The PCM5252 integrates ROM components of TI’s PurePath™ Smart Amp technology, which allows speakers to be driven with more peak power than their average-power rating, without damage to the speaker by voice coil over excursion or thermal overload.

The PCM5252 provides 4.2VRMS ground-centered differential outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single supply line drivers.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Block diagrams for the can be found at Functional Block Diagram.

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類型 標題 日期
* Data sheet PCM5252 Purepath™ Smart Amp 4.2-VRMS DirectPath, 114-dB Audio Stereo Differential-Output DAC with 32-bit, 384-kHz PCM Interface datasheet PDF | HTML 2014年 11月 20日

設計與開發

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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一,涵蓋我們的類比和電源產品組合,以及特定類比行為模型,且使用無需支付費用。

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參考設計

TIDA-01414 — TPA3244 Dolby Atmos 條型音箱參考設計

TPA3244 Dolby Atmos® 條型音箱參考設計結合了 Ultra-HD 音訊與高動態範圍,可透過小型系統創造充斥空間的音訊體驗。此設計運用 TI 的高性能 TPA3244 放大器,具有處理功能的 PCM5252 高性能 DAC,以及用於解碼和呈現 Dolby Atmos® 的整合式 SoC。條型音箱參考電路板使用 TI 的整合式音訊 DSP,提供 10 個 DAC + 放大器通道,以進行獨立通道處理,其中包括數位主動交越、DRC 和雙二階,以支援 5.1.2 條型音箱輸出配置。此設計使用 66AK2G 音訊 SoC 進行 Dolby Atmos® 解碼和轉譯。
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RHB) 32 Ultra Librarian

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