產品詳細資料

DSP (max) (MHz) 66 Rating Military Operating temperature range (°C) -55 to 125
DSP (max) (MHz) 66 Rating Military Operating temperature range (°C) -55 to 125
CFP (HFG) 132 585.1561 mm² 24.19 x 24.19 CFP (HFG) 132 582.2569 mm² 24.13 x 24.13 CPGA (GFA) 141 725.2249 mm² 26.93 x 26.93
  • Military Operating Temperature Range:
      55°C to 125°C
  • Processed to MIL-PRF-38535
  • Fast Instruction Cycle Time (30 ns and 40 ns)
  • Source-Code Compatible With All C1x and C2x Devices
  • RAM-Based Operation
    • 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM
    • 1056 × 16-Bit Dual-Access On-Chip Data RAM
  • 2K × 16-Bit On-Chip Boot ROM
  • 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
  • 32-Bit Arithmetic Logic Unit (ALU)
    • 32-bit Accumulator (ACC)
    • 32-Bit Accumulator Buffer (ACCB)
  • 16-Bit Parallel Logic Unit (PLU)
  • 16 × 16-Bit Multiplier, 32-Bit Product
  • 11 Context-Switch Registers
  • Two Buffers for Circular Addressing
  • Full-Duplex Synchronous Serial Port
  • Time-Division Multiplexed Serial Port (TDM)
  • Timer With Control and Counter Registers
  • 16 Software Programmable Wait-State Generators
  • Divide-by-One Clock Option
  • IEEE 1149.1 Boundary Scan Logic
  • Operations Are Fully Static
  • Enhanced Performance Implanted CMOS (EPIC™) Technology Fabricated by Texas Instruments
  • Packaging
    • 141-Pin Ceramic Grid Array (GFA Suffix)
    • 132-Lead Ceramic Quad Flat Package (HFG Suffix)
    • 132-Lead Plastic Quad Flat Package (PQ Suffix)

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC is a trademark of Texas Instruments Incorporated.

  • Military Operating Temperature Range:
      55°C to 125°C
  • Processed to MIL-PRF-38535
  • Fast Instruction Cycle Time (30 ns and 40 ns)
  • Source-Code Compatible With All C1x and C2x Devices
  • RAM-Based Operation
    • 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM
    • 1056 × 16-Bit Dual-Access On-Chip Data RAM
  • 2K × 16-Bit On-Chip Boot ROM
  • 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)
  • 32-Bit Arithmetic Logic Unit (ALU)
    • 32-bit Accumulator (ACC)
    • 32-Bit Accumulator Buffer (ACCB)
  • 16-Bit Parallel Logic Unit (PLU)
  • 16 × 16-Bit Multiplier, 32-Bit Product
  • 11 Context-Switch Registers
  • Two Buffers for Circular Addressing
  • Full-Duplex Synchronous Serial Port
  • Time-Division Multiplexed Serial Port (TDM)
  • Timer With Control and Counter Registers
  • 16 Software Programmable Wait-State Generators
  • Divide-by-One Clock Option
  • IEEE 1149.1 Boundary Scan Logic
  • Operations Are Fully Static
  • Enhanced Performance Implanted CMOS (EPIC™) Technology Fabricated by Texas Instruments
  • Packaging
    • 141-Pin Ceramic Grid Array (GFA Suffix)
    • 132-Lead Ceramic Quad Flat Package (HFG Suffix)
    • 132-Lead Plastic Quad Flat Package (PQ Suffix)

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC is a trademark of Texas Instruments Incorporated.

The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-um double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.

A number of enhancements to the basic SMJ320C2x architecture give the C50 a minimum 2× performance over the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.

The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 uA. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.

The C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time, and 66 MHz, providing a 30-ns cycle time. The available options are listed in Table 1.

The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-um double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.

A number of enhancements to the basic SMJ320C2x architecture give the C50 a minimum 2× performance over the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.

The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 uA. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.

The C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time, and 66 MHz, providing a 30-ns cycle time. The available options are listed in Table 1.

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技術文件

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類型 標題 日期
* Data sheet SMJ320C50/SMQ320C50 Digital Signal Processors datasheet (Rev. B) 2001年 9月 30日
* SMD SMJ320C50 SMD 5962-94558 2016年 6月 21日
User guide TMS320C5x Evaluation Module Installation Guide (Rev. C) 1996年 9月 1日
Application note Improving 32-Channel DTMF Decoders in PBX Systems Using the TMS320C5x DSP 1996年 6月 1日
User guide TMS320C5x DSP Starter Kit User's Guide (Rev. A) 1996年 6月 1日
Application note Use of the TMS320C5x Internal Oscillator With External Crystals or Resonators 1995年 7月 1日
Application note A PCMCIA TMS320 DSP MediaCard for Sound and Fax/Modem Applications 1995年 3月 1日
User guide TMS320C5x Emulator Installation Guide (Rev. B) 1994年 12月 1日
Application note Setting Up TMS320 DSP Interrupts in 'C' 1994年 11月 1日
Application note Minimizing Quantization Effects Using the TMS320 DSP Family 1994年 7月 1日
Application note Telecommunications Applications With the TMS320C5x 1994年 3月 1日
User guide TMS320C5x C Source Debugger User's Guide (Rev. B) 1994年 2月 1日
Application note Calculation Of TMS320C5x Power Dissipation 1993年 4月 1日
User guide Parallel Debug Mgr Addendum to TMS320C4x & TMS320C5x C Source Debugger UGs 1993年 4月 1日

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模擬型號

SM320C50, SMJ320C50, and SMQ320C50 BSDL Model

SGUM005.ZIP (4 KB) - BSDL Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
CFP (HFG) 132 Ultra Librarian
CFP (HFG) 132 Ultra Librarian
CPGA (GFA) 141 Ultra Librarian

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  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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