SN54AS825A
- Functionally Equivalent to AMD's AM29825
- Improved IOH Specifications
- Multiple Output Enables Allow Multiuser Control of the Interface
- Outputs Have Undershoot-Protection Circuitry
- Power-Up High-Impedance State
- Buffered Control Inputs Reduce dcLoading Effects
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing multiuser registers, I/O ports, bidirectional bus drivers, and working registers.
With the clock-enable (
)
input low, the eight D-type edge-triggered flip-flops enter data on
the low-to-high transitions of the clock (CLK) input. Taking high disables the clock buffer,
latching the outputs. These devices have noninverting data (D)
inputs. Taking the clear (
)
input low causes the eight Q outputs to go low independently of the
clock.
Multiuser buffered output-enable (
,
, and 
) inputs can be used to place the
eight outputs in either a normal logic state (high or low logic
level) or a high-impedance state. In the high-impedance state, the
outputs neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide the capability to
drive bus lines without interface or pullup components.
The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AS825A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS825A is characterized for operation from 0°C to 70°C.
= H if any of
OE1\, OE2\, or OE3\ are high.
= L if all of
OE1\, OE2\, or OE3\ are low.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit Bus-Interface Flip-Flops With 3-State Outputs datasheet (Rev. B) | 1995年 8月 1日 | |
| * | SMD | SN54AS825A SMD 5962-90780 | 2016年 6月 21日 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
| Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
| Application note | Advanced Schottky Load Management | 1997年 2月 1日 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
| Application note | Live Insertion | 1996年 10月 1日 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
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