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邏輯元件和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

SN54HCT74

現行

具有清除和預設功能的二路 D 型正緣觸發正反器

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產品規格表

SN54HCT74

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm² 19.56 x 6.67 CFP (W) 14 58.023 mm² 9.21 x 6.3 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Operating voltage range of 4.5 V to 5.5 V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max I CC
  • Typical t pd = 17 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max
  • Inputs are TTL-voltage compatible
  • Operating voltage range of 4.5 V to 5.5 V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max I CC
  • Typical t pd = 17 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max
  • Inputs are TTL-voltage compatible

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
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* Data sheet SNx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flips With Clear and Preset datasheet (Rev. G) PDF | HTML 2022年 10月 21日

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

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