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SN54SC8T595-SEP

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耐輻射 1.2V 至 5.5V 八位元移位暫存器

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產品規格表

SN54SC8T595-SEP

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產品規格表 立即訂購

產品詳細資料

Technology family SCxT Number of channels 8 Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs Input type TTL-Compatible CMOS Output type 3-State, Push-Pull Operating temperature range (°C) -55 to 125
Technology family SCxT Number of channels 8 Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs Input type TTL-Compatible CMOS Output type 3-State, Push-Pull Operating temperature range (°C) -55 to 125
TSSOP (PW) 16 32 mm² 5 x 6.4
  • VID TBD
  • Radiation Tolerant:
    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm2/mg at 125°C
    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)
    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm2/mg

  • Wide operating range of 1.2V to 5.5V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2V to 1.8V

      • 1.5V to 2.5V

      • 1.8V to 3.3V

      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mA per JESD 17
  • Space enhanced plastic:
    • Controlled baseline
    • Au bondwire and NiPdAu lead finish
    • Meets NASA ASTM E595 outgassing specification
    • One fabrication, assembly, and test site
    • Extended product life cycle
    • Product traceability
  • VID TBD
  • Radiation Tolerant:
    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm2/mg at 125°C
    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)
    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm2/mg

  • Wide operating range of 1.2V to 5.5V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2V to 1.8V

      • 1.5V to 2.5V

      • 1.8V to 3.3V

      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mA per JESD 17
  • Space enhanced plastic:
    • Controlled baseline
    • Au bondwire and NiPdAu lead finish
    • Meets NASA ASTM E595 outgassing specification
    • One fabrication, assembly, and test site
    • Extended product life cycle
    • Product traceability

The SN54SC8T595-SEP device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable ( OE) input is high, the outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN54SC8T595-SEP device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable ( OE) input is high, the outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
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類型 標題 日期
* Data sheet SN54SC8T595-SEP Radiation Tolerant 8-Bit Shift Registers With 3-State Output And Logic Level Shifter datasheet PDF | HTML 2024年 3月 5日
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 2024年 9月 10日

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