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SN74ABTH25245

現行

具有 3 態輸出的 25-Ohm 八路匯流排收發器

立即訂購
產品規格表

SN74ABTH25245

現行
產品規格表 立即訂購

產品詳細資料

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 188 IOH (max) (mA) -80 Input type TTL Output type TTL Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 188 IOH (max) (mA) -80 Input type TTL Output type TTL Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Designed to Facilitate Incident-Wave Switching for Line Impedances of 25 or Greater
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) DIPs

EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Designed to Facilitate Incident-Wave Switching for Line Impedances of 25 or Greater
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) DIPs

EPIC-IIB is a trademark of Texas Instruments Incorporated.

The 'ABTH25245 are 25- octal bus transceivers designed for asynchronous communication between data buses. They improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.

These devices allow noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can disable the device so that both buses are effectively isolated. When OE\ is low, the device is active.

These transceivers are capable of sinking 188 mA of IOL current, which facilitates switching 25- transmission lines on the incident wave. The distributed VCC and GND pins minimize switching noise for more-reliable system operation.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABTH25245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH25245 is characterized for operation from -40°C to 85°C.

The 'ABTH25245 are 25- octal bus transceivers designed for asynchronous communication between data buses. They improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.

These devices allow noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can disable the device so that both buses are effectively isolated. When OE\ is low, the device is active.

These transceivers are capable of sinking 188 mA of IOL current, which facilitates switching 25- transmission lines on the incident wave. The distributed VCC and GND pins minimize switching noise for more-reliable system operation.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABTH25245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH25245 is characterized for operation from -40°C to 85°C.

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類型 標題 日期
* Data sheet 25-Ohm Octal Bus Transceivers With 3-State Outputs datasheet (Rev. F) 1997年 5月 1日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 2004年 2月 16日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997年 3月 1日
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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