產品詳細資料

Function Counter Bits (#) 4 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Function Counter Bits (#) 4 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4
  • Carry Output for n-Bit Cascading
  • Buffer-Type Outputs Drive Bus Lines Directly
  • Choice of Asynchronous or Synchronous Clearing and Loading
  • Internal Look-Ahead Circuitry for Fast Cascading
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
  • Carry Output for n-Bit Cascading
  • Buffer-Type Outputs Drive Bus Lines Directly
  • Choice of Asynchronous or Synchronous Clearing and Loading
  • Internal Look-Ahead Circuitry for Fast Cascading
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). ACLR\ (direct clear) overrides all other functions of the device, while SCLR\ overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD\) or by the combination of a low level at synchronous load (SLOAD\) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR\, ALOAD\, SCLR\, and SLOAD\ are all high.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE\. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because CCO does not become active until the clock returns to the low level.

The SN54ALS561A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C.

 

 

These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). ACLR\ (direct clear) overrides all other functions of the device, while SCLR\ overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD\) or by the combination of a low level at synchronous load (SLOAD\) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR\, ALOAD\, SCLR\, and SLOAD\ are all high.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE\. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because CCO does not become active until the clock returns to the low level.

The SN54ALS561A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C.

 

 

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類型 標題 日期
* Data sheet Synchronous 4-Bit Counters With 3-State Outputs datasheet (Rev. A) 1995年 1月 1日
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024年 4月 30日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Advanced Schottky (ALS and AS) Logic Families 1995年 8月 1日

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