SN74AUP1G80
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typical at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot <10% of VCC
- Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typical at 3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.4 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. F) | PDF | HTML | 2017年 7月 20日 |
| Selection guide | Logic Guide (Rev. AC) | PDF | HTML | 2025年 11月 13日 | |
| Application brief | Understanding Schmitt Triggers (Rev. B) | PDF | HTML | 2025年 4月 17日 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |
| Selection guide | Little Logic Guide 2018 (Rev. G) | 2018年 7月 6日 | ||
| Application note | Designing and Manufacturing with TI's X2SON Packages | 2017年 8月 23日 | ||
| Application note | How to Select Little Logic (Rev. A) | 2016年 7月 26日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 |
設計與開發
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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
5-8-NL-LOGIC-EVM — 支援 5 至 8 針腳 DPW、DQE、DRY、DSF、DTM、DTQ 和 DTT 封裝的通用邏輯和轉譯 EVM
支援任何具 DTT、DRY、DPW、DTM、DQE、DQM、DSF 或 DTQ 封裝的邏輯或轉換裝置之通用 EVM。可實現靈活評估的電路板設計。
TIDA-01056 — 最小化 EMI 的同時最佳化電源供應效率的 20 位元 1MSPS DAQ 參考設計
TIDA-01054 — 用於消除高效能 DAQ 系統中的 EMI 影響的多軌電源參考設計
TIDA-01055 — 適用於高效能 DAQ 系統的 ADC 電壓參考緩衝器最佳化參考設計
TIDA-01057 — 將真正 10Vpp 差分輸入的訊號動態範圍最大化至 20 位元 ADC 的參考設計
TIDA-01051 — 針對自動測試設備最佳化 FPGA 利用率和數據處理能力的參考設計
TIDA-01050 — 適用於 18 位元 SAR 資料轉換器的最佳化類比前端 DAQ 系統參考設計
TIDA-01052 — 使用負電源輸入改進全幅 THD 的 ADC 驅動器參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| DSBGA (YFP) | 6 | Ultra Librarian |
| SOT-23 (DBV) | 5 | Ultra Librarian |
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
| USON (DRY) | 6 | Ultra Librarian |
| X2SON (DPW) | 5 | Ultra Librarian |
| X2SON (DSF) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點