SN74AUP2G07

Name: SN74AUP2G07
Brand: TI
SKU: SN74AUP2G07
Price: 0.06 USD

現行

具開汲極輸出的 2 通道、0.8-V 至 3.6-V 低功耗緩衝器

立即訂購

產品規格表

document-pdfAcrobat SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E) (英文) PDF | HTML

SN74AUP2G07

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

0.9

IOH (max) (mA)

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

0.9

IOH (max) (mA)

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YFP)

1.4000000000000001 mm² 1 x 1.4000000000000001

SOT-SC70 (DCK)

4.2 mm² 2 x 2.1

USON (DRY)

1.45 mm² 1.45 x 1

X2SON (DSF)

1 mm² 1 x 1

Low static-power consumption (I_CC = 0.9 µA maximum)
Low dynamic-power consumption (C_pd = 1 pF typical at 3.3 V)
Low input capacitance (C_i = 1.5 pF typical)
Low noise – overshoot and undershoot <10% of V_CC
I_off supports live insertion, partial-power-down mode, and back-drive protection
Input hysteresis allows slow input transition and better switching noise immunity at the input (V_hys = 250 mV typical at 3.3 V)
Wide operating V_CC range of 0.8 V to 3.6 V
Optimized for 3.3 V operation
3.6-V I/O tolerant to support mixed-mode signal operation
t_pd = 3.3 ns maximum at 3.3 V
Suitable for point-to-point applications
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD performance tested per JESD 22
- 4500-V human-body model
- 1500-V charged-device model

Low static-power consumption (I_CC = 0.9 µA maximum)
Low dynamic-power consumption (C_pd = 1 pF typical at 3.3 V)
Low input capacitance (C_i = 1.5 pF typical)
Low noise – overshoot and undershoot <10% of V_CC
I_off supports live insertion, partial-power-down mode, and back-drive protection
Input hysteresis allows slow input transition and better switching noise immunity at the input (V_hys = 250 mV typical at 3.3 V)
Wide operating V_CC range of 0.8 V to 3.6 V
Optimized for 3.3 V operation
3.6-V I/O tolerant to support mixed-mode signal operation
t_pd = 3.3 ns maximum at 3.3 V
Suitable for point-to-point applications
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD performance tested per JESD 22
- 4500-V human-body model
- 1500-V charged-device model

The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V.

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現行

具有開漏輸出的 2 通道、1.65-V 至 5.5-V 緩衝器 Larger voltage range (1.65V to 5.5V), higher drive average drive strength (24mA)

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	類型	標題		日期
*	Data sheet	SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E)	PDF \| HTML	2021年 10月 4日
	Application brief	Understanding Schmitt Triggers (Rev. A)	PDF \| HTML	2019年 5月 22日
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)		2016年 7月 26日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日