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SN74CBTLV3257-EP

現行

強化型產品低電壓 4 位元 2 選 1 FET 多工器/解多工器

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產品規格表

SN74CBTLV3257-EP

現行
產品規格表 立即訂購

產品詳細資料

Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 2:1 SPDT Number of channels 4 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -55 to 125 Crosstalk (dB) No ESD CDM (kV) 0.2 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.5 OFF-state leakage current (max) (µA) 15 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating HiRel Enhanced Product
Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 2:1 SPDT Number of channels 4 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -55 to 125 Crosstalk (dB) No ESD CDM (kV) 0.2 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.5 OFF-state leakage current (max) (µA) 15 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating HiRel Enhanced Product
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm)
  • Controlled baseline
    • One assembly site
    • One test site
    • One fabrication site
  • Extended temperature performance of –55°C to 125°C
  • Enhanced diminishing manufacturing sources (DMS) support
  • Enhanced product-change notification
  • Qualification pedigree (1)
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled baseline
    • One assembly site
    • One test site
    • One fabrication site
  • Extended temperature performance of –55°C to 125°C
  • Enhanced diminishing manufacturing sources (DMS) support
  • Enhanced product-change notification
  • Qualification pedigree (1)
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current does not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current does not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74CBTLV3257-EP Low-Voltage 4-Bit 1-of-2 FET Multiplexer/Demultiplexer datasheet (Rev. A) PDF | HTML 2019/5/6
* VID SN74CBTLV3257-EP VID V6208615 2016/6/21
應用說明 Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/6/2
應用說明 Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/1

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