TXE8148
- Functional Safety-Capable
- Operating supply voltage range of 1.65V to 5.5V
- Low standby current consumption of 6µA typical
- 10MHz SPI SCLK frequency
- SPI daisy-chain supported
- SPI read and write with burst mode
- Multi-port SPI command to configure multiple ports simultaneously
- IOFF supported input port pins
- Active-low reset input (RESET)
- Open-drain active-low interrupt output (INT)
- Interrupt mask and status per I/O
- Interrupt status per port
- Built-in fail safe I/O feature
- Individual I/O configuration for:
- Input and output function
- Polarity inversion
- Output push-pull and open-drain selection
- Integrated pullup or pulldown selection
- Bus-hold feature to maintain last I/O state
- Glitch filter enable selection
- Latched outputs with 10mA drive capability for directly driving LEDs
- Latch-up performance exceeds 100mA per AEC Q100-004
- Latch-up performance exceeds 100mA per JESD 78, class II
The TXE8148 device provides general purpose parallel input/output (I/O) expansion for the four wire Serial Peripheral Interface (SPI) protocol and is designed for 1.65V to 5.5V VCC operation. The SPI protocol supports standard point-to-point communication along with daisy-chaining of multiple TXE8148.
The device supports SPI bus frequency of 10MHz from 1.65V to 5.5V. I/O expanders such as the TXE8148 provide a simple design when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and so on.
The TXE8148 has six I/O ports each with eight IOs per port, which include additional features designed to enhance the I/O performance in terms of speed, power consumption and EMI. These features include per I/O programmable open-drain or push-pull outputs, programmable pullup and pulldown resistors, bus-hold latchable inputs, maskable interrupt, interrupt status register, and a fail-safe register mode which is enabled by the FAIL-SAFE pin.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | TXE8148 48-Bit SPI Bus I/O Expander With Interrupt Output, Reset Input, and I/O Configuration Registers datasheet | PDF | HTML | 2026年 6月 26日 |
| Functional safety information | TXE8148 Functional Safety FIT Rate, FMD and Pin FMA | PDF | HTML | 2026年 5月 8日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
TINA-TI — 基於 SPICE 的類比模擬程式
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|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。