The ADC32RF45 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital conver (ADC) with the JESD204B interface. The EVM includes the ADC32RF45 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages.
The input for each channel of the ADC is, by default, connected to a transformer input circuit, which can be connected to a 50-Ω single-ended signal source. The clock reference input is provided via a transformer input and can be connected to a 50-Ω single-ended clock source. An onboard LMK04828 can be used to generate the necessary JESD204B clocks. Configuration register access is provided through the onboard USB connection and a Windows®-based GUI. An industry-standard JESD204B pin assignment on an FMC connector allows direct connection to the TSW14J56 Capture Card, as well as many commercially available FPGA development platforms.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | EVM User's guide | ADC32RFxxEVM User's Guide (Rev. E) | 31 Jan 2020 | |
| Certificate | ADC32RF45EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| More literature | Arria10 + ADC32RF44 Design | 06 Dec 2017 | ||
| More literature | KCU105 + ADC32RF44 Design Firmware | 06 Dec 2017 | ||
| Technical article | Push your receiver bandwidths past 1-GHz in high-end applications | 26 May 2016 |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.