ADC32RF45 evaluation module for dual-channel, 14-bit, 3-GSPS, RF-sampling ADC


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The ADC32RF45 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital conver (ADC) with the JESD204B interface. The EVM includes the ADC32RF45 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages.

The input for each channel of the ADC is, by default, connected to a transformer input circuit, which can be connected to a 50-Ω single-ended signal source. The clock reference input is provided via a transformer input and can be connected to a 50-Ω single-ended clock source. An onboard LMK04828 can be used to generate the necessary JESD204B clocks. Configuration register access is provided through the onboard USB connection and a Windows®-based GUI. An industry-standard JESD204B pin assignment on an FMC connector allows direct connection to the TSW14J56 Capture Card, as well as many commercially available FPGA development platforms.



  • Onboard clock generation, or external clocking supported with LMK04828 generating SYSREF
  • JESD204B data interface to simplify digital interface; compliant up to 12.3-Gbps lane rates
  • Onboard power management with TI


  • ADC32RF45 EVM
  • USB cable
  • Power cable

High-speed ADCs (>10MSPS)
ADC32RF45 Dual-channel, 14-bit, 3-GSPS, RF-sampling analog-to-digital converter (ADC)


Clock jitter cleaners & synchronizers
LMK04828 Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.


RF PLLs & synthesizers
LMX2582 5.5-GHz high performance, wideband PLLatinum RF synthesizer

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Evaluation board

ADC32RF45EVM – ADC32RF45 evaluation module for dual-channel, 14-bit, 3-GSPS, RF-sampling ADC

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Design files

ADC32RFxxEVM Design Package SBAC147.ZIP (7034 KB)

Technical documentation

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Type Title Date
* User guide ADC32RFxxEVM User's Guide (Rev. E) Jan. 31, 2020
Certificate ADC32RF45EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
More literature Arria10 + ADC32RF44 Design Dec. 06, 2017
More literature KCU105 + ADC32RF44 Design Firmware Dec. 06, 2017
Technical article Push your receiver bandwidths past 1-GHz in high-end applications May 26, 2016

Related design resources

Hardware development

TSW14J56EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps TSW14J57EVM Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

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