Product details

Number of input channels 2 Resolution (Bits) 14 Sample rate (max) (Msps) 3000 Features Decimating Filter, Ultra High Speed Analog input BW (MHz) 3200 SFDR (dB) 66 SNR (dB) 61.1 Power consumption (typ) (mW) 6400 Operating temperature range (°C) -40 to 85 Rating Catalog
Number of input channels 2 Resolution (Bits) 14 Sample rate (max) (Msps) 3000 Features Decimating Filter, Ultra High Speed Analog input BW (MHz) 3200 SFDR (dB) 66 SNR (dB) 61.1 Power consumption (typ) (mW) 6400 Operating temperature range (°C) -40 to 85 Rating Catalog
VQFN (RRH) 72 100 mm² 10 x 10 VQFNP (RMP) 72 100 mm² 10 x 10
  • 14-Bit, Dual-Channel, 3-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.1 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • 14-Bit, Dual-Channel, 3-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.1 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF8x supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF8x supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

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Technical documentation

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* Data sheet ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices datasheet (Rev. B) PDF | HTML 21 Dec 2021
Application note Spurs Analysis in the RF Sampling ADC 09 Feb 2018
Application note Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) 05 Sep 2017
Design guide Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design 23 Sep 2016
Application note RF Sampling ADC with 800MHz of IBW LTE 08 Sep 2016
White paper Analog advancements make waves in 5G communications 12 Aug 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC32RF80EVM — ADC32RF80 evaluation module for dual-channel, 14-bit, 3-GSPS, RF-sampling wideband receiver

The ADC32RF80 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF80 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)

User guide: PDF
Not available on TI.com
GUI for evaluation module (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

Supported products & hardware

GUI for evaluation module (EVM)

SBAC148 ADC32RFxxEVM SPI GUI Installer

Supported products & hardware

Supported products & hardware

Simulation model

ADC32RF45 IBIS Model

SBAM273.ZIP (46 KB) - IBIS Model
Simulation model

ADC32RF45 IBIS-AMI Model

SBAM274.ZIP (3109 KB) - IBIS-AMI Model
Calculation tool

FREQ-DDC-FILTER-CALC RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

Supported products & hardware

Supported products & hardware

Reference designs

TIDEP0081 — Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design

For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
VQFN (RRH) 72 Ultra Librarian
VQFNP (RMP) 72 Ultra Librarian

Ordering & quality

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