Dual-Channel, 14-Bit, 1.5-GSPS RF-Sampling Analog-to-Digital Converter (ADC)
Product details
Parameters
Package | Pins | Size
Features
- 14-Bit, Dual-Channel, 1.5-GSPS ADC
- Noise Floor: –151.8 dBFS/Hz
- RF Input Supports Up to 4 GHz
- Aperture Jitter: 90 fS
- Channel Isolation: 95 dB at fIN = 1.8 GHz
- Spectral Performance (fIN = 950 MHz, –2 dBFS):
- SNR: 61.1 dBFS
- SFDR: 67-dBc HD2, HD3
- Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
- SNR: 58.9 dBFS
- SFDR: 64-dBc HD2, HD3
- On-Chip Digital Down-Converters:
- Up to 4 DDCs (Dual-Band Mode)
- Up to 3 Independent NCOs per DDC
- On-Chip Input Clamp for Overvoltage Protection
- Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
- On-Chip Dither
- On-Chip Input Termination
- Input Full-Scale: 1.35 VPP
- Support for Multi-Chip Synchronization
- JESD204B Interface:
- Subclass 1-Based Deterministic Latency
- 4 Lanes Per Channel Up to 12.5 Gbps
- Power Dissipation: 2 W/Ch at 1.5 GSPS
- 72-Pin VQFN Package (10 mm × 10 mm)
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Description
The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | ADC32RF42 Dual-Channel, 14-Bit, 1.5-GSPS, Analog-to-Digital Converter datasheet | May 16, 2017 |
Technical article | Keys to quick success using high-speed data converters | Oct. 13, 2020 | |
User guide | ADC32RFxxEVM User's Guide (Rev. E) | Jan. 31, 2020 | |
Technical article | How to achieve fast frequency hopping | Mar. 03, 2019 | |
Application note | Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) | Sep. 05, 2017 | |
Technical article | RF sampling: Learning more about latency | Feb. 09, 2017 | |
Technical article | Why phase noise matters in RF sampling converters | Nov. 28, 2016 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The ADC32RF42 evaluation module (EVM) demonstrates the performance of a dual 1.5-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF42 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)
Features
- External clocking supported, or onboard clock generation with LMK04828 generating SYSREF
- JESD204B data interface to simplify digital interface; compliant up to 12.5-Gbps lane rates
- Onboard power management with TI
Software development
Features
- Compatible with JEDEC JESD204a/b/c protocols
- Supports subclass 1 deterministic latency and multidevice synchronization
- Supported lane rates
- Up to 16.375 Gbps in 8b/10b mode
- Up to 20 Gbps in 64b/66b mode
- Supports all protocol related error detection and reporting features
- Integrated transport layer (...)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
In the concept phase, a frequency-planning tool enables fine tuning of both (...)
Features
- Frequency planning
- Analog filtering
- Decimation filter spur location
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RMP) | 72 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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