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ADC32RF42

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Dual-Channel, 14-Bit, 1.5-GSPS RF-Sampling Analog-to-Digital Converter (ADC)

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Data sheet

ADC32RF42

ACTIVE
Data sheet Order now

Product details

Sample rate (Max) (MSPS) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.35 Power consumption (Typ) (mW) 4000 Architecture Pipeline SNR (dB) 63 ENOB (Bits) 9.9 SFDR (dB) 70 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.35 Power consumption (Typ) (mW) 4000 Architecture Pipeline SNR (dB) 63 ENOB (Bits) 9.9 SFDR (dB) 70 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



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Technical documentation

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Type Title Date
* Data sheet ADC32RF42 Dual-Channel, 14-Bit, 1.5-GSPS, Analog-to-Digital Converter datasheet PDF | HTML 16 May 2017
EVM User's guide ADC32RFxxEVM User's Guide (Rev. E) 31 Jan 2020
Application note Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) 05 Sep 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC32RF42EVM — ADC32RF42 Dual-Channel, 14-Bit, 1.5GSPS, RF-Sampling ADC Evaluation Module

The ADC32RF42 evaluation module (EVM) demonstrates the performance of a dual 1.5-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF42 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)

User guide: PDF
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Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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GUI for evaluation module (EVM)

ADC32RFxxEVM SPI GUI Installer (Rev. B)

SBAC148B.ZIP (179936 KB)
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Simulation model

ADC32RF45 IBIS Model

SBAM273.ZIP (46 KB) - IBIS Model
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Simulation model

ADC32RF45 IBIS-AMI Model

SBAM274.ZIP (3109 KB) - IBIS-AMI Model
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Calculation tool

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Package Pins Download
VQFN (RMP) 72 View options

Ordering & quality

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