ADC32RF45

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Dual-Channel, 14-Bit, 3-GSPS RF-Sampling Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 3000 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.35 Power consumption (Typ) (mW) 6400 Architecture Pipeline SNR (dB) 63 ENOB (Bits) 10 SFDR (dB) 77 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFNP (RMP) 72 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • 14-Bit, Dual-Channel, 3.0-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 77-dBc Worst Spur
  • Spectral Performance (fIN = 1.78 GHz, –2 dBFS):
    • SNR: 58.8 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 75-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet ADC32RF45 Dual-Channel, 14-Bit, 3.0-GSPS, Analog-to-Digital Converter datasheet (Rev. C) Dec. 06, 2016
User guides ADC32RFxxEVM User's Guide (Rev. E) Jan. 31, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Application notes Spurs Analysis in the RF Sampling ADC Feb. 09, 2018
User guides TSW40RF8x Evaluation Module User's Guide (Rev. A) Sep. 27, 2017
Application notes Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) Sep. 05, 2017
Application notes Designing a modern power supply for RF sampling converters Apr. 26, 2017
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
User guides Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design Sep. 23, 2016
Application notes RF Sampling ADC with 800MHz of IBW LTE Sep. 08, 2016
Application notes ADC32RF45: Amplifier to ADC Interface (Rev. A) Sep. 07, 2016
White papers Analog advancements make waves in 5G communications Aug. 12, 2016
Application notes How unmatched impedance at the clock input of an RF ADC affects SNR and jitter Jul. 21, 2016
Application notes Clocking Optimization for RF Sampling Analog-to-Digital Converters May 17, 2016
Application notes S-Parameters for ADC32RF45: Modeling and Application May 16, 2016
Application notes Implementing JESD204B SYSREF and Achieving Deterministic Latency with ADC32RF45 May 10, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADC32RF45 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital conver (ADC) with the JESD204B interface. The EVM includes the ADC32RF45 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages (...)

Features

 

  • Onboard clock generation, or external clocking supported with LMK04828 generating SYSREF
  • JESD204B data interface to simplify digital interface; compliant up to 12.3-Gbps lane rates
  • Onboard power management with TI

 

EVALUATION BOARDS Download
document-generic User guide
2499
Description

The TSW40RF80 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF80 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The DAC38RF80 (...)

Features
  • RF-sampling transceiver utilizing the JESD204B interface
  • DAC38RF80 dual RF DAC with single-ended output
  • ADC32RF45 dual RF ADC with bypass option
  • LDO-less power-management solution
  • Onboard clocking solution; four different ADC clocking options, including TX PLL clock output
  • Interfaces with TSW14J56 or (...)
EVALUATION BOARDS Download
document-generic User guide
2499
Description

The TSW40RF82 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF82 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The DAC38RF82 (...)

Features
  • RF-sampling transceiver utilizing the JESD204B interface
  • DAC38RF82 dual RF DAC with differential output
  • ADC32RF45 dual RF ADC with bypass option
  • LDO-less power-management solution
  • Onboard clocking solution; four different ADC clocking options, including TX PLL clock output
  • Interfaces with TSW14J56 or FPGA (...)
GUIS FOR EVALUATION MODULES (EVM) Download
SBAC148B.ZIP (179936 KB)

Design tools & simulation

SIMULATION MODELS Download
SBAM273.ZIP (46 KB) - IBIS Model
SIMULATION MODELS Download
SBAM274.ZIP (3109 KB) - IBIS-AMI Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOLS Download
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)

Features
  • Frequency planning
  • Analog filtering
  • Decimation filter spur location
GERBER FILES Download
SBAC147.ZIP (7034 KB)

Reference designs

REFERENCE DESIGNS Download
High-Bandwidth Zero-IF Reference Design for Microwave Backhaul
TIDA-01435 — The TSW40RF82EVM reference design provides a platform to interface the DAC38RF82 with a high-performance modulator - the TRF370417EVM. The TRF370417EVM can modulate wideband signals at up to 6 GHz as would be typical for a microwave backhaul application. The TRF370417 device may be substituted for a (...)
document-generic Schematic document-generic User guide
Design files
REFERENCE DESIGNS Download
Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers
TIDA-01016 — TIDA-01016 is a clocking solution for high dynamic range high speed ADC. RF input signals are directly captured using the RF sampling approach by high speed ADC. The ADC32RF45 is a dual- channel, 14-bit, 3-GSPS RF sampling ADC. The 3-dB input bandwidth is 3.2 GHz, and it captures signals up to 4 GHz (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
1-GHz Signal Bandwidth RF Sampling Receiver Reference Design
TIDA-01161 — The RF sampling architecture offers an alternative to the traditional super-heterodyne architecture. An RF sampling analog-to-digital converter (ADC) operates at a high sampling rate and converts signals directly from radio frequencies (RF) to digital. Because of the high sampling rate, the RF (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-band RF Sampling Receiver Reference Design
TIDA-01163 — The RF sampling receiver captures signals directly in the radio frequency (RF) band. In a multi-band application the desired signals are not very wide band but they are spaced far apart within the spectrum. The reference design captures signals in different RF bands and digitally down-converts them (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Efficient, LDO-Less, Power-Supply Network Reference Design for RF-Sampling ADC
TIDA-01247 TI Design TIDA-01247 demonstrates a simplified and efficient network to power an ADC32RFxx. All three power domains of the analog-to-digital converter (ADC) are supplied using a switching regulator to enable the use of a power-supply network without a low-dropout (LDO) linear regulator (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
RF-Sampling S-Band Radar Receiver Reference Design
TIDA-00814 — A direct RF sampling receiver approach to a radar system operating in S-band is demonstrated using the ADC32RF45, 3-Gsps, 14-bit analog to digital converter (ADC). RF sampling reduces the complexity of a system by removing down conversion and using a high sampling rate enables wider signal (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RMP) 72 View options

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