Product details

Sample rate (Max) (MSPS) 3000 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.35 Power consumption (Typ) (mW) 6400 Architecture Pipeline SNR (dB) 63 ENOB (Bits) 10 SFDR (dB) 77 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 3000 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.35 Power consumption (Typ) (mW) 6400 Architecture Pipeline SNR (dB) 63 ENOB (Bits) 10 SFDR (dB) 77 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 14-Bit, Dual-Channel, 3.0-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 77-dBc Worst Spur
  • Spectral Performance (fIN = 1.78 GHz, –2 dBFS):
    • SNR: 58.8 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 75-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • 14-Bit, Dual-Channel, 3.0-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 77-dBc Worst Spur
  • Spectral Performance (fIN = 1.78 GHz, –2 dBFS):
    • SNR: 58.8 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 75-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

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Technical documentation

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Type Title Date
* Data sheet ADC32RF45 Dual-Channel, 14-Bit, 3.0-GSPS, Analog-to-Digital Converter datasheet (Rev. C) 06 Dec 2016
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Application note Clocking Optimization for RF Sampling Analog-to-Digital Converters (Rev. A) 07 Apr 2021
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
User guide ADC32RFxxEVM User's Guide (Rev. E) 31 Jan 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Application note Spurs Analysis in the RF Sampling ADC 09 Feb 2018
User guide TSW40RF8x Evaluation Module User's Guide (Rev. A) 27 Sep 2017
Application note Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) 05 Sep 2017
Analog design journal Designing a modern power supply for RF sampling converters 26 Apr 2017
Technical article RF sampling: Learning more about latency 09 Feb 2017
Design guide Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design 23 Sep 2016
Application note RF Sampling ADC with 800MHz of IBW LTE 08 Sep 2016
Application note ADC32RF45: Amplifier to ADC Interface (Rev. A) 07 Sep 2016
White paper Analog advancements make waves in 5G communications 12 Aug 2016
Analog design journal How unmatched impedance at the clock input of an RF ADC affects SNR and jitter 21 Jul 2016
Application note S-Parameters for ADC32RF45: Modeling and Application 16 May 2016
Application note Implementing JESD204B SYSREF and Achieving Deterministic Latency with ADC32RF45 10 May 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC32RF45EVM — ADC32RF45 evaluation module for dual-channel, 14-bit, 3-GSPS, RF-sampling ADC

The ADC32RF45 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital conver (ADC) with the JESD204B interface. The EVM includes the ADC32RF45 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)

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Evaluation board

TSW40RF80EVM — 2T2R RF-Sampling Transceiver w/ Dual 14-Bit 3GSPS ADC/9GSPS DAC Clocking Solution Evaluation Module

The TSW40RF80 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF80 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The (...)

In stock
Limit: 3
Evaluation board

TSW40RF82EVM — 2T2R RF-Sampling Transceiver w/ Dual 14-Bit 3GSPS ADC/9GSPS DAC Clocking Solution Evaluation Module

The TSW40RF82 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF82 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The (...)

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Limit: 3
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
GUI for evaluation module (EVM)

ADC32RFxxEVM SPI GUI Installer (Rev. B)

SBAC148B.ZIP (179936 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADC32RF45 IBIS Model

SBAM273.ZIP (46 KB) - IBIS Model
Simulation model

ADC32RF45 IBIS-AMI Model

SBAM274.ZIP (3109 KB) - IBIS-AMI Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

Gerber file

ADC32RFxxEVM Design Package

SBAC147.ZIP (7034 KB)
Reference designs

TIDA-01435 — High-Bandwidth Zero-IF Reference Design for Microwave Backhaul

The TSW40RF82EVM reference design provides a platform to interface the DAC38RF82 with a high-performance modulator - the TRF370417EVM. The TRF370417EVM can modulate wideband signals at up to 6 GHz as would be typical for a microwave backhaul application. The TRF370417 device may be substituted for (...)
Reference designs

TIDA-01247 — Efficient, LDO-Less, Power-Supply Network Reference Design for RF-Sampling ADC

This reference design demonstrates a simplified and efficient network to power an ADC32RFxx. All three power domains of the analog-to-digital converter (ADC) are supplied using a switching regulator to enable the use of a power-supply network without a low-dropout (LDO) linear regulator. (...)
Reference designs

TIDA-01161 — 1-GHz Signal Bandwidth RF Sampling Receiver Reference Design

The RF sampling architecture offers an alternative to the traditional super-heterodyne architecture. An RF sampling analog-to-digital converter (ADC) operates at a high sampling rate and converts signals directly from radio frequencies (RF) to digital. Because of the high sampling rate, the RF (...)
Reference designs

TIDA-01163 — Multi-band RF Sampling Receiver Reference Design

The RF sampling receiver captures signals directly in the radio frequency (RF) band. In a multi-band application the desired signals are not very wide band but they are spaced far apart within the spectrum. The reference design captures signals in different RF bands and digitally down-converts them (...)
Reference designs

TIDA-01016 — Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers

TIDA-01016 is a clocking solution for high dynamic range high speed ADC. RF input signals are directly captured using the RF sampling approach by high speed ADC. The ADC32RF45 is a dual- channel, 14-bit, 3-GSPS RF sampling ADC. The 3-dB input bandwidth is 3.2 GHz, and it captures signals up to 4 (...)
Reference designs

TIDA-00814 — RF-Sampling S-Band Radar Receiver Reference Design

A direct RF sampling receiver approach to a radar system operating in S-band is demonstrated using the ADC32RF45, 3-Gsps, 14-bit analog to digital converter (ADC). RF sampling reduces the complexity of a system by removing down conversion and using a high sampling rate enables wider signal (...)
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