ADC32RF82

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Dual-channel, 14-bit, 2.45-GSPS, RF-sampling telecom receiver and feedback IC

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Product details

Parameters

Number of input channels 2 Resolution (Bits) 14 Sample rate (Max) (MSPS) 2456 Features Decimating Filter, Ultra High Speed Analog input BW (MHz) 3200 SFDR (Typ) (dB) 67 SNR (Typ) (dB) 61.2 Power consumption (Typ) (mW) 5500 Logic voltage DV/DD (Max) (V) 1.2 Logic voltage DV/DD (Min) (V) 1.1 Analog voltage AVDD (Max) (V) 1.25, 2 Analog voltage AVDD (Min) (V) 1.1, 1.8 Operating temperature range (C) -40 to 85 open-in-new Find other Receivers

Package | Pins | Size

VQFNP (RMP) 72 100 mm² 10 x 10 open-in-new Find other Receivers

Features

  • 14-Bit, Dual-Channel, 2457.6-MSPS ADC
  • Noise Floor: –154.1 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 61.2 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 81-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.7 dBFS
    • SFDR: 71-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.0 W/Ch at 2457.6 MSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

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Description

The ADC32RF82 is a 14-bit, 2457.6-MSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF82 delivers a noise spectral density of –154.1 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF82 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet ADC32RF82 Dual-Channel, 2457.6-MSPS Telecom Receiver and Feedback Device datasheet Sep. 19, 2017
User guides ADC32RFxxEVM User's Guide (Rev. E) Jan. 31, 2020
Application notes Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) Sep. 05, 2017
Technical articles Why should you care about the noise immunity of MLVDS drivers and receivers? Jul. 26, 2017
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Technical articles RF sampling: analog-to-digital converter linearity sets sensitivity Sep. 29, 2016
Technical articles RF sampling: linearity performance is not so straightforward Aug. 30, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADC32RF82 evaluation module (EVM) demonstrates the performance of a dual, 2.45-GSPS, 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF82 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the (...)

Features
  • External clocking supported or onboard clock generation with LMK04828-generating SYSREF
  • JESD204B data interface simplifies digital interface; compliant up to 12.5-GBPS lane rates
  • Onboard power management with Texas Instruments
GUIS FOR EVALUATION MODULES (EVM) Download
SBAC148B.ZIP (179936 KB)

Design tools & simulation

SIMULATION MODELS Download
SBAM273.ZIP (46 KB) - IBIS Model
CALCULATION TOOLS Download
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)

Features
  • Frequency planning
  • Analog filtering
  • Decimation filter spur location

CAD/CAE symbols

Package Pins Download
VQFN (RMP) 72 View options

Ordering & quality

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