TIDA-00432

Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems

TIDA-00432

Design files

Overview

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.

Features
  • Demonstrates a typical phased array radar sub-system by showing synchronization of JESD204B giga-sample ADCs
  • The LMK04828 clocking solution used is described in detail
  • Test results show synchronization within 50 ps without any characterization of cables or calibration of propagation delays
  • Xilinx firmware development is discussed to offer a clear understanding of the requirements
  • This sub-system is tested and includes example configuration files

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU752.PDF (2321 K)

Reference design overview and verified performance test data

TIDRDI4.PDF (555 K)

Detailed schematic diagram for design layout and components

TIDRDI5.PDF (140 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDC978.ZIP (712 K)

Design file that contains information on physical board layer of design PCB

Products

Includes TI products in the design and potential alternatives.

High-speed ADCs (>10MSPS)

ADC12J160012-Bit, 1.6-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet document-pdfAcrobat PDF open-in-new HTML
High-speed ADCs (>10MSPS)

ADC12J270012-Bit, 2.7-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet document-pdfAcrobat PDF open-in-new HTML
High-speed ADCs (>10MSPS)

ADC12J400012-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet document-pdfAcrobat PDF open-in-new HTML
Buck converters (integrated switch)

LM26400YDual 2A, 500kHz Wide Input Range Buck Regulator

Data sheet document-pdfAcrobat PDF open-in-new HTML
Buck converters (integrated switch)

TPS543274.5V to 18V Input, 3-A Synchronous Step-Down Converter

Data sheet document-pdfAcrobat PDF open-in-new HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

LP38513-ADJ3-A, adjustable ultra-low-dropout voltage regulator with low-noise & enable

Data sheet document-pdfAcrobat PDF
Linear & low-dropout (LDO) regulators

LP3878-ADJ800-mA, 16-V, adjustable low-dropout voltage regulator with enable

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet document-pdfAcrobat PDF open-in-new HTML
Linear & low-dropout (LDO) regulators

TPS749013-A, low-VIN (0.8-V), adjustable ultra-low-dropout voltage regulator with power good & enable

Data sheet document-pdfAcrobat PDF open-in-new HTML

Start development

Software

IDE, configuration, compiler or debugger

TIDA-00432 Configuration Files – TIDC979.ZIP (11 K)

Technical documentation

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Type Title Date
Design guide Synchronization of JESD204B Giga-Sample ADCs Jan. 20, 2015

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