Product details

Output options Adjustable Output Iout (Max) (A) 3 Vin (Max) (V) 5.5 Vin (Min) (V) 0.8 Vout (Max) (V) 3.6 Vout (Min) (V) 0.8 Noise (uVrms) 20 Iq (Typ) (mA) 3 Thermal resistance θJA (°C/W) 34 Rating Catalog Load capacitance (Min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power Good, Soft Start Accuracy (%) 2 PSRR @ 100 KHz (dB) 28 Dropout voltage (Vdo) (Typ) (mV) 120 Operating temperature range (C) -40 to 125
Output options Adjustable Output Iout (Max) (A) 3 Vin (Max) (V) 5.5 Vin (Min) (V) 0.8 Vout (Max) (V) 3.6 Vout (Min) (V) 0.8 Noise (uVrms) 20 Iq (Typ) (mA) 3 Thermal resistance θJA (°C/W) 34 Rating Catalog Load capacitance (Min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power Good, Soft Start Accuracy (%) 2 PSRR @ 100 KHz (dB) 28 Dropout voltage (Vdo) (Typ) (mV) 120 Operating temperature range (C) -40 to 125
TO-263 (KTW) 7 154 mm² 10.1 x 15.24 VQFN (RGW) 20 25 mm² 5.0 x 5.0 VQFN (RGW) 20 25 mm² 5 x 5 VSON (DRC) 10 9 mm² 3 x 3
  • VOUT Range: 0.8 V to 3.6 V
  • Ultralow VIN Range: 0.8 V to 5.5 V
  • VBIAS Range: 2.7 V to 5.5 V
  • Low Dropout: 120 mV (Typical) at 3 A
  • Power-Good (PG) Output Allows Supply Monitoring or Provides a Sequencing Signal for Other Supplies
  • 2% Accuracy Over Line, Load, and Temperature
  • Adjustable Start-Up In-Rush Control
  • VBIAS Permits Low VIN Operation With Good Transient Response
  • Stable with Any Output Capacitor ≥ 2.2 µF
  • Packages:
    • Small, 3-mm × 3-mm × 1-mm VSON
    • 5-mm × 5-mm × 1-mm VQFN and DDPAK-7
  • Active High Enable
  • VOUT Range: 0.8 V to 3.6 V
  • Ultralow VIN Range: 0.8 V to 5.5 V
  • VBIAS Range: 2.7 V to 5.5 V
  • Low Dropout: 120 mV (Typical) at 3 A
  • Power-Good (PG) Output Allows Supply Monitoring or Provides a Sequencing Signal for Other Supplies
  • 2% Accuracy Over Line, Load, and Temperature
  • Adjustable Start-Up In-Rush Control
  • VBIAS Permits Low VIN Operation With Good Transient Response
  • Stable with Any Output Capacitor ≥ 2.2 µF
  • Packages:
    • Small, 3-mm × 3-mm × 1-mm VSON
    • 5-mm × 5-mm × 1-mm VQFN and DDPAK-7
  • Active High Enable

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and well-suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2 µF, and the device is fully specified from –40°C to 125°C. The TPS74901 is offered in a small (3 mm × 3 mm) VSON package and a small (5-mm × 5-mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and well-suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2 µF, and the device is fully specified from –40°C to 125°C. The TPS74901 is offered in a small (3 mm × 3 mm) VSON package and a small (5-mm × 5-mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.

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Technical documentation

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Type Title Date
* Data sheet TPS74901 3-A Low Dropout Linear Regulator With Programmable Soft-Start datasheet (Rev. I) 03 May 2016
Technical article 3 quiescent-current (Iq) specifications you need to understand 12 Nov 2021
Application note LDO Noise Demystified (Rev. B) 18 Aug 2020
Application note A Topical Index of TI LDO Application Notes (Rev. F) 27 Jun 2019
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 21 Mar 2018
Application note LDO PSRR Measurement Simplified (Rev. A) 09 Aug 2017
Analog design journal Q2 2009 Issue Analog Applications Journal 01 May 2009
Analog design journal Taming linear-regulator inrush currents 01 May 2009
User guide TPS74901EVM-210 (Rev. B) 24 Jul 2008
User guide TPS74901EVM-210 14 Apr 2007

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS74901EVM-210 — TPS74901EVM-210 Evaluation Module

The TPS74901EVM-210 facilitates evaluation of the TPS74901 low-dropout linear regulator IC.

These regulators require a low-power bias voltage, VBIAS, and a power input voltage, VIN. The regulator is capable of providing output voltages down to 0.8 V, output currents up to 3 A and has an (...)

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Simulation model

TPS74901 Unencrypted PSpice Transient Model

SBVM634.ZIP (3 KB) - PSpice Model
Simulation model

TPS74901 PSpice Transient Model (Rev. B)

SLIM031B.ZIP (60 KB) - PSpice Model
Simulation model

TPS74901 TINA-TI Transient Spice Model

SLIM256.ZIP (35 KB) - TINA-TI Spice Model
Simulation model

TPS74901 TINA-TI Transient Reference Design

SLIM257.TSC (94 KB) - TINA-TI Spice Model
Reference designs

TIDA-00431 — RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier

Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

Reference designs

TIDA-01017 — High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars

The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)
Reference designs

TIDA-01015 — 4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers

The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input (...)
Reference designs

TIDA-00826 — 50-Ohm 2-GHz Oscilloscope Front-end Reference Design

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Reference designs

TIDA-00432 — Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
Reference designs

TIDA-00359 — Clocking Solution Reference Design for GSPS ADCs

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
Package Pins Download
DDPAK/TO-263 (KTW) 7 View options
VQFN (RGW) 20 View options
VSON (DRC) 10 View options

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