Product details


Output options Adjustable Output Iout (Max) (A) 3 Vin (Max) (V) 5.5 Vin (Min) (V) 0.8 Vout (Max) (V) 3.6 Vout (Min) (V) 0.8 Noise (uVrms) 20 Iq (Typ) (mA) 3 Thermal resistance θJA (°C/W) 34 Load capacitance (Min) (µF) 2.2 Rating Catalog Regulated outputs (#) 1 Features Enable, Power Good, Soft Start Accuracy (%) 2 PSRR @ 100 KHz (dB) 28 Dropout voltage (Vdo) (Typ) (mV) 120 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

TO-263 (KTW) 7 154 mm² 10.1 x 15.24 VQFN (RGW) 20 25 mm² 5 x 5 VSON (DRC) 10 9 mm² 3 x 3 open-in-new Find other Linear regulators (LDO)


  • VOUT Range: 0.8 V to 3.6 V
  • Ultralow VIN Range: 0.8 V to 5.5 V
  • VBIAS Range: 2.7 V to 5.5 V
  • Low Dropout: 120 mV (Typical) at 3 A
  • Power-Good (PG) Output Allows Supply Monitoring or Provides a Sequencing Signal for Other Supplies
  • 2% Accuracy Over Line, Load, and Temperature
  • Adjustable Start-Up In-Rush Control
  • VBIAS Permits Low VIN Operation With Good Transient Response
  • Stable with Any Output Capacitor ≥ 2.2 µF
  • Packages:
    • Small, 3-mm × 3-mm × 1-mm VSON
    • 5-mm × 5-mm × 1-mm VQFN and DDPAK-7
  • Active High Enable
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The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and well-suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2 µF, and the device is fully specified from –40°C to 125°C. The TPS74901 is offered in a small (3 mm × 3 mm) VSON package and a small (5-mm × 5-mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.

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Similar but not functionally equivalent to the compared device:
TPS7A84 ACTIVE 3-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy TPS7A84 is the next-generation version of this device with lower noise.

Technical documentation

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Type Title Date
* Datasheet TPS74901 3-A Low Dropout Linear Regulator With Programmable Soft-Start datasheet (Rev. I) May 03, 2016
Application note LDO Noise Demystified (Rev. B) Aug. 18, 2020
Application note A Topical Index of TI LDO Application Notes (Rev. F) Jun. 27, 2019
Technical article LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical article LDO Basics: Preventing reverse current Jul. 25, 2018
Technical article LDO basics: introduction to quiescent current Jun. 20, 2018
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) Mar. 21, 2018
Application note LDO PSRR Measurement Simplified (Rev. A) Aug. 09, 2017
Technical article LDO basics: noise – part 1 Jun. 14, 2017
Application note Q2 2009 Issue Analog Applications Journal May 01, 2009
Application note Taming linear-regulator inrush currents May 01, 2009
User guide TPS74901EVM-210 (Rev. B) Jul. 24, 2008
User guide TPS74901EVM-210 Apr. 14, 2007

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The TPS74901EVM-210 facilitates evaluation of the TPS74901 low-dropout linear regulator IC.

These regulators require a low-power bias voltage, VBIAS, and a power input voltage, VIN. The regulator is capable of providing output voltages down to 0.8 V, output currents up to 3 A and has an (...)

  • Soft-Start pin provides a linear startup with ramp time set by external capacitor
  • 2% accuracy over line, load and temperature
  • Supports input voltages as low as 0.9 V with external bias supply
  • Adjustable output (0.8 V to 3.6 V)
  • Ultra-low dropout: 120 mV at 3.0 A (typical)
  • Stable with any output capacitor (...)

Design tools & simulation

SBVM634.ZIP (3 KB) - PSpice Model
SLIM031B.ZIP (60 KB) - PSpice Model
SLIM256.ZIP (35 KB) - TINA-TI Spice Model
SLIM257.TSC (94 KB) - TINA-TI Spice Model

Reference designs

RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
TIDA-00431 Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

document-generic Schematic document-generic User guide
High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars
TIDA-01017 — The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)
document-generic Schematic document-generic User guide
4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers
TIDA-01015 — The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input bandwidth (...)
document-generic Schematic document-generic User guide
50-Ohm 2-GHz Oscilloscope Front-end Reference Design
TIDA-00826 This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
document-generic Schematic document-generic User guide
Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432 This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
document-generic Schematic document-generic User guide
Clocking Solution Reference Design for GSPS ADCs
TIDA-00359 Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
DDPAK/TO-263 (KTW) 7 View options
VQFN (RGW) 20 View options
VSON (DRC) 10 View options

Ordering & quality

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