12 Revision History
Changes from August 18, 2023 to December 15, 2023 (from Revision A (AUGUST 2023) to Revision B (DECEMBER 2023))
-
Global: Changed the document product status from "Advance
Information" to "Production Data"Go
- (Features): Updated GPU bullets.Go
- (Applications): Added Industrial header to the Applications End
Equipment listsGo
- (Detailed Description/ Functional Block Diagram): Updated image (MMAv2,
DMPAC under Multimedia )Go
- (Device Comparison): AM6954 added. AM6934 removed.Go
- (Device Comparison): DMPAC feature added.Go
- (Device Comparison): Deleted the "Hyperlink is not supported on this
SoC. System designs …" footnote and associated cross-referenceGo
- (Pin Attributes Header List): Added "Low: and High: states to the
TX (Output Buffer) for the "BALL STATE DURING RESET
(RX/TX/PULL)"Go
- (Pin Attributes): Added missing Signal Type fields for VMON* and VPP*
signals.Go
- (Pin Attributes): Added "The MUXMODE field is not used to select …" footnote for the
WKUP_GPIO0_[71:86] signals in the Pin Attributes (ALY Package)
tableGo
- (Pin Attributes): Added Ball State DURING Reset and Ball State AFTER Reset
information for MMC0_* pins in the Pin Attributes (ALY Package)
tableGo
- (Pin Attributes): Deleted the HYP_*, HYP0_*, HYP1_* signals from the Pin
Attributes (ALY Package) table (not supported)Go
- (EFUSE Signal Descriptions): Added PIN TYPE fields to the
tableGo
- (VMON Signal Descriptions): Added PIN TYPE fields to the
tableGo
- (ROC for OTP eFuse Programming): Removed legacy PMIC part number
from footnote.Go
- (Combined MCU and Main Domains Power- Up Sequencing): Updated note that
starts with "VDD_MCU is a digital voltage domain …" to clarify VDD_MCU grouping and
sequence constraints.Go
- (Isolated MCU and Main Domains Power-Up Sequencing): Updated note that
starts with "VDD_MCU is a digital voltage domain …" to clarify VDD_MCU grouping and
sequence constraints.Go
- (HyperBus): Added the MIN and MAX values for CL, Output
load capacitance in the HyperBus Timing Conditions table, under OUTPUT
CONDITIONSGo
- (MMC1/2 - SD/SDIO Interface/ UHS–I DDR50 Mode): Updated/Changed the
fop(clk), Operating frequency, MMC[x]_CLK MAX value from "40" to
"50" MHzGo
- (MMC1/2 - SD/SDIO Interface/ UHS–I DDR50 Mode): Updated/Changed the
DDR505, tc(clk), Cycle time, MMC[x]_CLK MIN value from "25" to "20"
nsGo
- (OSPI Switching Characteristics – Data Training):
Added MAX values to the tc(CLK), Cycle time, CLK
for DDR 1.8 V, 3.3 V and SDR 1.8 V, 3.3 V
modesGo
- (Detailed Description/ Functional Block Diagram): Updated image (MMAv2,
DMPAC under Multimedia )Go
- (Device Naming Convention): Added the AM6954 VALUE to the base
production part number choices and removed the AM6934 part
numberGo