SBOS671D September   2018  – December 2022 OPA2828 , OPA828

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Phase-Reversal Protection
      2. 7.3.2  Electrical Overstress
      3. 7.3.3  MUX Friendly Inputs
      4. 7.3.4  Overload Power Limiter
      5. 7.3.5  Noise Performance
        1. 7.3.5.1 Low Noise
      6. 7.3.6  Capacitive Load and Stability
      7. 7.3.7  Settling Time
      8. 7.3.8  Slew Rate
      9. 7.3.9  Full-Power Bandwidth
      10. 7.3.10 Small-Signal Response
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Low Offset Voltage Drift
      13. 7.3.13 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 SAR ADC Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Pass Filter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
        2. 8.4.1.2 PowerPAD™ Design Considerations (DGN package only)
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, (V+) = 15 V, (V–) = –15 V, VCM = VO = midsupply, CL = 20 pF, and RL = 2 kΩ connected to midsupply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage D package ±50 ±300 µV
TA = 0°C to 85°C ±350
TA = –40°C to +125°C ±400
DGN package ±25 ±125
TA = 0°C to 85°C ±175
TA = –40°C to 125°C ±200
dVOS/dT Input offset voltage drift TA = 0°C to +85°C ±0.3 ±1.3 µV/°C
TA = –40°C to +125°C D package ±0.45 ±1.5
DGN package ±0.2 ±0.8
PSRR Power-supply rejection ratio 8 V ≤ VS ≤ 36 V 1.4 ±5.6 µV/V
TA = 0°C to 85°C ±7
TA = –40°C to +125°C ±10
INPUT BIAS CURRENT
IB Input bias current D package ±1 ±8 pA
DGN package ±0.2 ±5
TA = 0°C to 85°C ±400
TA = –40°C to +125°C ±3 nA
IOS Input offset current D package ±1 ±8 pA
DGN package ±0.2 ±5
TA = 0°C to 85°C ±500
TA = –40°C to +125°C ±1.5 nA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz, peak-to-peak 0.34 µVPP
f = 0.1 Hz to 10 Hz, RMS 0.06 µVRMS
eN Input voltage noise density f = 10 Hz 7.5 nV/√Hz
f = 100 Hz 4.8
f = 1 kHz 4
iN Input current noise density f = 1 kHz 1.2 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage (V–) + 2.5 (V+) – 3.5 V
CMRR Common-mode rejection ratio (V–) + 2.5 V < VCM < (V+) – 3.5 V D package 108 115 dB
DGN package 103 108 dB
(V–) + 2.5 V < VCM < (V+) – 3.5 V,
TA = 0°C to 85°C		 D package 105 dB
DGN package 102 dB
(V–) + 2.5 V < VCM < (V+) – 3.5 V,
TA = –40°C to +125°C		 D package 103 dB
DGN package 100 dB
INPUT IMPEDANCE
ZID Differential 1012 || 6 Ω || pF
ZICM Common-mode 1012 || 9 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 1.6 V< VO < (V+) – 1.6 V, RL = 600 Ω 120 130 dB
(V–) + 1.5 V < VO < (V+) – 1.5 V, RL = 10 kΩ 120 130
TA = 0°C to 85°C (V–) + 1.6 V< VO < (V+) – 1.6 V, RL = 600 Ω 117
(V–) + 1.5 V < VO < (V+) – 1.5 V, RL = 10 kΩ 118
TA = –40°C to +125°C (V–) + 1.6 V< VO < (V+) – 1.6 V, RL = 600 Ω 114
(V–) + 1.5 V < VO < (V+) – 1.5 V, RL = 10 kΩ 114
FREQUENCY RESPONSE
Unity gain frequency VO = 10 mVPP, CL = 30 pF 45 MHz
Phase margin VO = 10 mVPP, CL = 30 pF 57 Degrees
GBW Gain-bandwidth product VO = 10 mVPP, CL = 30 pF 45 MHz
SR Slew rate VO = 10-V step G = +1 150 V/µs
G = –1 150
tS Settling time (input to output) VO = 10-V step, CL = 30 pF, G = –1 To ±0.0244%
(12-bit accuracy)		 110 ns
To ±0.0061%
(14-bit accuracy)		 120
Overshoot VO = 100-mV step, G = +1, CL = 30 pF VO = 100-mV step,
G = +1, CL = 30 pF		 8%
Overload recovery time G = –10 55 ns
THD+N Total harmonic distortion + noise VO = 3.5 VRMS, G = +1,
f = 1 kHz		 RL = 10 kΩ 0.000028 %
–130 dB
RL = 600 Ω 0.000028 %
–130 dB
HD2 Second-order harmonic distortion VO = 5 VPP, G = +1 f = 100 kHz 119 dBc
f = 500 kHz 90
HD3 Third-order harmonic distortion VO = 5 VPP, G = +1 f = 100 kHz 125 dBc
f = 500 kHz 105
IMD Second-order intermodulation distortion SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz), G = 1,
VO = 3 VRMS, RL = 2 kΩ, 9-kHz measurement bandwidth		 132 dB
Third-order intermodulation distortion CCIF twin-tone (19 kHz and 20 kHz), G = 1,
VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth		 137 dB
OUTPUT
Output voltage swing RL = 10 kΩ 0.9 1.2 V
RL = 600 Ω 1.2
IO Output current For linear operation, AOL ≥ 120 dB ±30 mA
ISC Short-circuit current ±50 mA
CL Capacitive load drive See Typical Characteristics Curves pF
ZO Open-loop output impedance f = 1 MHz, IO = 0 mA 13.5 Ω
POWER SUPPLY
IQ Quiescent current (per amplifier)   IO = 0 A 5.5 6.2 mA
TA = 0°C to 85°C 7.1
TA = –40°C to +125°C 7.9