SLAS666B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
For lower power consumption, the best process is to derive the internal audio processing clocks using the simple dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing clocks then using the on-board PLL is necessary. The fractional PLL generates an internal master clock that produces the processing clocks required by the DAC. The programmability of this PLL allows operation from a wide variety of clocks that may be available in the system.
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register-programmable to enable generation of the required sampling rates with fine resolution. The PLL turns on by writing to page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock, PLL_CLK, is given by Equation 6.
where
The PLL turns on through page 0 / register 5, bit D7. The variable P is programmed through page 0 / register 5, bits D6–D4. The variable R is programmed through page 0 / register 5, bits D3–D0. The variable J is programmed through page 0 / register 6, bits D5–D0. The variable D is 14 bits and is programmed into two registers. The MSB portion is programmed through page 0 / register 7, bits D5–D0, and the LSB portion is programmed thrugh page 0 / register 8, bits D7–D0. For proper update of the D-divider value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. The new value of D does not take effect unless the write to page 0 / register 8 is complete.
When the PLL is enabled, the following conditions must be satisfied:
80 MHz ≤ (PLL_CLKIN × J.D. × R / P) ≤ 110 MHz
4 ≤ R × J ≤ 259
80 MHz ≤ PLL_CLKIN × J.D. × R / P ≤ 110 MHz
R = 1
The PLL can power up independently from the DAC block, and can also be used as a general-purpose PLL by routing the PLL output to the GPIO output. After powering up the PLL, PLL_CLK is available typically after 10 ms.
The clocks for the codec and various signal processing blocks, CODEC_CLKIN, are generated from the MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).
If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last.
Table 6-28 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to achieve a sample rate fS of either 44.1 kHz or 48 kHz.
PLL_CLKIN (MHz) | PLLP | PLLR | PLLJ | PLLD | MDAC | NDAC | DOSR |
---|---|---|---|---|---|---|---|
fS = 44.1 kHz | |||||||
2.8224 | 1 | 3 | 10 | 0 | 3 | 5 | 128 |
5.6448 | 1 | 3 | 5 | 0 | 3 | 5 | 128 |
12 | 1 | 1 | 7 | 560 | 3 | 5 | 128 |
13 | 1 | 1 | 6 | 3504 | 6 | 3 | 104 |
16 | 1 | 1 | 5 | 2920 | 3 | 5 | 128 |
19.2 | 1 | 1 | 4 | 4100 | 3 | 5 | 128 |
48 | 4 | 1 | 7 | 560 | 3 | 5 | 128 |
fS = 48 kHz | |||||||
2.048 | 1 | 3 | 14 | 0 | 7 | 2 | 128 |
3.072 | 1 | 4 | 7 | 0 | 7 | 2 | 128 |
4.096 | 1 | 3 | 7 | 0 | 7 | 2 | 128 |
6.144 | 1 | 2 | 7 | 0 | 7 | 2 | 128 |
8.192 | 1 | 4 | 3 | 0 | 4 | 4 | 128 |
12 | 1 | 1 | 7 | 1680 | 7 | 2 | 128 |
16 | 1 | 1 | 5 | 3760 | 7 | 2 | 128 |
19.2 | 1 | 1 | 4 | 4800 | 7 | 2 | 128 |
48 | 4 | 1 | 7 | 1680 | 7 | 2 | 128 |