SLAS666B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
The audio interface of the can enter the right-justified mode by programming page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.
For the right-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data.