JAJSSJ5 December 2023 DRV8234
PRODUCTION DATA
Table 7-36 lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in Table 7-36 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
9h | CONFIG0 | Configuration Registers - Faults (1/5). | Section 7.6.2.1 |
Ah | CONFIG1 | Configuration Registers - (2/5). | Section 7.6.2.2 |
Bh | CONFIG2 | Configuration Registers - (3/5). | Section 7.6.2.3 |
Ch | CONFIG3 | Configuration Registers - (4/5). | Section 7.6.2.4 |
Dh | CONFIG4 | Configuration Registers - (5/5). | Section 7.6.2.5 |
Complex bit access types are encoded to fit into small table cells. Table 7-37 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CONFIG0 is shown in Table 7-38.
Return to the Summary Table.
Enable/Disable various faults like OCP, OVP, STALL, etc.
CONFIG1 is shown in Table 7-39.
Return to the Summary Table.
Configure the inrush time (1/2).
CONFIG2 is shown in Table 7-40.
Return to the Summary Table.
Configure the inrush time (2/2).
CONFIG3 is shown in Table 7-41.
Return to the Summary Table.
Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time.
CONFIG4 is shown in Table 7-42.
Return to the Summary Table.
Configure the report registers like RC_REP and STALL_REP.