JAJSSJ5 December 2023 DRV8234
PRODUCTION DATA
For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency.
The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.
When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.
If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased.
If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased.
During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity.
During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge.
If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver.
The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation.
Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle.
Bit | Value |
---|---|
0b | 25 kHz |
1b | 50 kHz |
In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b.