JAJSRI9A October 2023 – March 2024 LM51772
ADVANCE INFORMATION
To maintain fixed voltage and interface programmable voltage the device contains an internal voltage divider. In this case the FB is not applicable for sensing the output voltage for the loop regulation. Instead the VOUT-pin is used to sense the output voltage on the power stage.
The device detects via the FB-pin if it shall operate with an external or internal voltage divider. If the voltage on the FB-pin is higher than VT+(SEL,iFB), before the soft-start is initiated, if the part should operate with a internal or external feedback. The selection of internal and external FB cannot be done dynamically and the pin information gets latched until the next EN or V(POR) power cycle.
The resolution of the programming can be changed with the SEL_DIV20 bit.
If the V_OUT register read back is used the low voltage clamping will be done with whatever SEL_DIV20 value is programmed at this time. If SEL_DIV20 is updated after VOUT_A, the clamping might not be correct anymore. To guarantee correct clamping its recommended to (re-)write VOUT_A after changing SEL_DIV20 bit.
Below an overview of the possible Vo setting according the VOUT_A and SEL_DIV20
Parameter | Value |
---|---|
Output voltage min. | 3.3V |
Output voltage max. | 24V |
Output voltage programming step size typ. | 10mV |
You can use the following equation to calculate the nominal output voltage:
Parameter | Value |
---|---|
Output voltage min. | 3.3V |
Output voltage max | 48V |
Output voltage programming step size typ. | 20mV |
The read-out register value of the 'VOUT_A' control register is clamped for the lower and for the upper limit of the register range.
You can use the following equation to calculate the nominal output voltage: