JAJSRI9A October 2023 – March 2024 LM51772
ADVANCE INFORMATION
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
V(VIN) | Input Voltage Sense | 0 | 48 | 55 | V |
V(BIAS) | Bias Input Voltage Supply | 0 | 40 | V | |
Input/Bias start-up voltage | 3.5 | V | |||
Minumum voltage for PCM operatoin | 6 | V | |||
V(VOUT) | Output Voltage Sense | 3.3 | 55 | V | |
V(ILIM) | ISNSP;ISNSN | 2.8 | 55 | V | |
R(ISNS) | current limit sens resistor | 10 | mΩ | ||
current limit sens resistor tolerance | –1 | 1 | % | ||
C(VCC2) | VCC regulator output capacitance | 6 | µF | ||
C(VCC1) | VCC regulator output capacitance | 2 | µF | ||
VFB | FB Input | 0 | V(VCC) | V | |
VIL | Logic pin low-level (MODE, DTRK, SYNC, SDA, SCL) | 0.4 | V | ||
VIH | Logic pin high-level (MODE, DTRK, SYNC, SDA, SCL) | 1.3 | V | ||
FSW | Typical Switching Frequency | 100 | 2200 | kHz | |
FSYNC | Synchronization switching Frequency range | 100 | 2200 | kHz | |
TJ | Operating Junction Temperature(2) | –40 | 125 | °C |