JAJSRI9A October 2023 – March 2024 LM51772
ADVANCE INFORMATION
The device features an internal phase looked loop (PLL), which is designed to transition the switching frequency seamlessly between the frequency set by the RT pin and the external frequency synchronization signal. If no external frequency is provided, the RT pin sets the center frequency of the PLL. The external synchronization signal can change the switching frequency ±50%. To ensure low quiescence current, the input buffer of the SYNC pin is disabled if no valid sync frequency, that is a frequency signal outside the recommended synchronization range is applied.
The f(SW) synchronization stops if the device enters power save mode or μSleep operation, if enabled. Once the converter enters the PWM operation again, the device re-syncs to a pin signal. The synchronization timings are given in Figure 8-20
The sync pin can be programmed through I2C or config pin CFG2 as input or output.