JAJSTE0 March 2024 LMK05318B-Q1
PRODUCTION DATA
Each reference input clock (PRIREF and SECREF) has the own 16-b reference divider to the DPLL TDC block. The R divider output of the selected reference sets the TDC input frequency. To support hitless switching between inputs with different frequencies, the R dividers can be used to divide the clocks to a single common frequency to the DPLL TDC input.