JAJSTE0 March 2024 LMK05318B-Q1
PRODUCTION DATA
When a loss-of-reference (LOR) condition is detected and no valid input is available, the PLL1 channel enters holdover mode. If the tuning word history is valid, the initial output frequency accuracy upon entry into holdover is pulled to the computed average frequency accuracy just prior to the loss of reference. If history is not valid (no history exists) and the DPLL_HLDOVR_MODE bit is 0, the holdover frequency accuracy is determined by the free-run tuning word register (user programmable). Otherwise, if history is not valid and DPLL_HLDOVR_MODE is 1, the DPLL holds the last digital loop filter output control value (which is not tuning word history).
If history is valid, the initial holdover frequency accuracy depends on the DPLL loop bandwidth and the elapsed time used for historical averaging. See Tuning Word History for more information. In general, the longer the historical average time, the more accurate the initial holdover frequency assuming the 0ppm reference clock (XO input) is drift-free. The stability of the XO reference clock determines the long-term stability and accuracy of the holdover output frequency. Upon entry into holdover, the LOPL flag is asserted (LOPL → 1). The LOFL flag is not asserted, however, as long as the holdover frequency accuracy does not drift beyond of the programmed loss-of-frequency-lock threshold. When a valid input becomes available for selection, the PLL1 channel exits holdover mode and automatically phase lock with the new input clock without any output glitches.