JAJSTE0 March 2024 LMK05318B-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY CHARACTERISTICS | ||||||
IDD_DIG | Core Current Consumption (VDD_DIG) |
21 | mA | |||
IDD_IN | Core Current Consumption (VDD_IN) |
43 | mA | |||
IDD_PLL1 | Core Current Consumption (VDD_PLL1) |
DPLL and APLL1 enabled | 110 | mA | ||
IDD_XO | Core Current Consumption (VDD_XO) |
20 | mA | |||
IDD_PLL2 | Core Current Consumption (VDD_PLL2) |
APLL2 disabled | 18.5 | mA | ||
APLL2 enabled | 120 | mA | ||||
IDDO_x | Output Current Consumption, per channel(3) (VDDO_x) |
Output mux and divider enabled, excludes driver Divider value = 2 to 6 |
65 | mA | ||
Output mux and divider enabled, excludes driver Divider value > 6 |
70 | mA | ||||
AC-LVDS | 11 | mA | ||||
AC-CML | 16 | mA | ||||
AC-LVPECL | 18 | mA | ||||
HCSL, 50Ω load to GND | 25 | mA | ||||
1.8V LVCMOS (x2), 100MHz | 4.7 | mA | ||||
IDDPDN | Total Current Consumption (all VDD and VDDO pins, 3.3V) | Device powered-down (PDN pin held low) | 56 | 75 | mA | |
XO INPUT CHARACTERISTICS (XO) | ||||||
fIN | Input frequency range | 10 | 100 | MHz | ||
VIN-SE | Single-ended input voltage swing | Single ended input, internal AC coupling | 0.4 | 2.6 | Vpp | |
VIN-DIFF | Differential input peak to peak voltage swing(16) | Differential input | 0.4 | 2 | Vpp | |
VID | Differential input voltage swing(12) | Differential input | 0.2 | 1 | |V| | |
dV/dt | Input slew rate(14) | 0.2 | 0.5 | V/ns | ||
IDC | Input duty cycle | 40 | 60 | % | ||
IIN | Input leakage | 50Ω and 100Ω internal terminations disabled | –350 | 350 | µA | |
REFERENCE INPUT CHARACTERISTICS (PRIREF, SECREF) | ||||||
fIN | Input frequency range | Differential input(4) | 5 | 800 | MHz | |
LVCMOS input | 1E–6 | 250 | MHz | |||
VIH | Input high voltage | DC-coupled input | 1.8 | V | ||
VIL | Input low voltage | DC-coupled input | 0.6 | V | ||
VIN-SE | Single-ended input voltage swing | AC-coupled input | 0.4 | 2.6 | Vpp | |
VIN-DIFF | Differential input peak to peak voltage swing(16) | Differential input, VHYST = 50mV | 0.4 | 2 | Vpp | |
Differential input, ,VHYST = 200mV | 0.7 | 2 | Vpp | |||
VID | Differential input voltage swing(12) | Differential input, VHYST = 50mV | 0.2 | 1 | V | |
Differential input, VHYST = 200mV | 0.35 | 1 | V | |||
dV/dt | Input slew rate(14) | 0.2 | 0.5 | V/ns | ||
IIN | Input leakage | 50Ω and 100Ω internal terminations disabled | –350 | 350 | µA | |
VCO CHARACTERISTICS | ||||||
fVCO1 | VCO1 Frequency Range | 2499.75 | 2500 | 2500.25 | MHz | |
fVCO2 | VCO2 Frequency Range | 5500 | 6250 | MHz | ||
|ΔTCL| | Allowable Temperature Drift for Continuous Lock | After programming for lock, no changes to output configuration are permitted to provide continuous lock | 125 | ℃ | ||
APLL CHARACTERISTICS | ||||||
fPD1 | APLL1 Phase Detector Frequency | 1 | 100 | MHz | ||
fPD2 | APLL2 Phase Detector Frequency | 12 | 150 | MHz | ||
tAPLL1-LOCK | APLL1 lock time(13) | Time between soft or hard reset and APLL1 output stable within ± 25ppm fXO = 48MHz, fPD1 = fXO/2 |
1.0 | ms | ||
tAPLL2-LOCK | APLL2 lock time(13) | Time between soft or hard reset and APLL2 output stable within ± 25ppm, fXO = 48MHz, fPD2 = fXO/2 |
2.5 | ms | ||
Time between soft or hard reset and APLL2 output stable within ± 25ppm, fXO = 48MHz, fPD2 = fVCO1/18 | 2.5 | ms | ||||
AC-LVDS OUTPUT CHARACTERISTICS (OUTx) | ||||||
fOUT | Output frequency(5) | 1250 | MHz | |||
VOD | Output voltage swing (VOH - VOL) | 25MHz ≤ fOUT ≤ 800MHz; TYP at 156.25MHz | 250 | 390 | 450 | mV |
fOUT = 50MHz | 285 | 400 | 450 | mV | ||
100MHz ≤ fOUT ≤ 200MHz | 275 | 390 | 450 | mV | ||
fOUT = 312.5MHz | 270 | 385 | 450 | mV | ||
fOUT = 625MHz | 250 | 310 | 450 | mV | ||
fOUT = 1250MHz | 280 | mV | ||||
VOUT-DIFF | Differential output voltage swing, peak-to-peak | 2×VOD | Vpp | |||
VOS | Output common mode | 100 | 430 | mV | ||
tSK | Output-to-output skew | Same post divider, output divide values, and output type | 100 | ps | ||
tR/tF | Output rise/fall time(13) | 20% to 80%, < 300MHz | 225 | 350 | ps | |
± 100mV around center point, 300MHz ≤ fOUT ≤ 800MHz | 85 | 250 | ps | |||
PNFLOOR | Output phase noise floor | fOUT = 156.25MHz; fOFFSET > 10MHz | -160 | dBc/Hz | ||
ODC | Output duty cycle(10) | 45 | 55 | % | ||
AC-CML OUTPUT CHARACTERISTICS (OUTx) | ||||||
fOUT | Output frequency(5) | 1250 | MHz | |||
VOD | Output voltage swing (VOH - VOL) | 25MHz ≤ fOUT ≤ 800MHz; TYP at fOUT = 156.25MHz | 400 | 600 | 800 | mV |
fOUT = 50MHz | 500 | 620 | 700 | mV | ||
100MHz ≤ fOUT ≤ 200MHz | 490 | 600 | 690 | mV | ||
fOUT = 312.5MHz | 480 | 580 | 680 | mV | ||
fOUT = 625MHz | 350 | 460 | 600 | mV | ||
fOUT = 1250MHz | 400 | mV | ||||
VOUT-DIFF | Differential output voltage swing, peak-to-peak | 2×VOD | Vpp | |||
VOS | Output common mode | 150 | 550 | mV | ||
tSK | Output-to-output skew | Same post divider, output divide values, and output type | 100 | ps | ||
tR/tF | Output rise/fall time(13) | 20% to 80%, < 300MHz | 225 | 300 | ps | |
± 100mV around center point, 300MHz ≤ fOUT ≤ 800MHz | 50 | 150 | ps | |||
PNFLOOR | Output phase noise floor | fOUT = 156.25MHz; fOFFSET > 10MHz | -160 | dBc/Hz | ||
ODC | Output duty cycle(10) | 45 | 55 | % | ||
AC-LVPECL OUTPUT CHARACTERISTICS (OUTx) | ||||||
fOUT | Output frequency(5) | 1250 | MHz | |||
VOD | Output voltage swing (VOH - VOL) | 25MHz ≤ fOUT ≤ 800MHz; TYP at fOUT = 156.25MHz | 450 | 780 | 1000 | mV |
fOUT = 50MHz | 660 | 810 | 920 | mV | ||
100MHz ≤ fOUT ≤ 200MHz | 640 | 780 | 900 | mV | ||
fOUT = 312.5MHz | 620 | 740 | 880 | mV | ||
fOUT = 625MHz | 500 | 620 | 760 | mV | ||
fOUT = 1250MHz | 510 | mV | ||||
VOUT-DIFF | Differential output voltage swing, peak-to-peak | 2×VOD | Vpp | |||
VOS | Output common mode | 300 | 700 | mV | ||
tSK | Output-to-output skew | Same post divider, output divide values, and output type | 100 | ps | ||
tR/tF | Output rise/fall time(13) | 20% to 80%, < 300MHz | 200 | 300 | ps | |
± 100mV around center point, 300MHz ≤ fOUT ≤ 800MHz | 35 | 100 | ps | |||
PNFLOOR | Output phase noise floor | fOUT = 156.25MHz; fOFFSET > 10MHz | –162 | dBc/Hz | ||
ODC | Output duty cycle(10) | 45 | 55 | % | ||
HCSL OUTPUT CHARACTERISTICS (OUTx) | ||||||
fOUT | Output frequency(5) | 625 | MHz | |||
VOH | Output high voltage | fOUT ≤ 400MHz | 600 | 880 | mV | |
fOUT = 625MHz | 500 | 800 | mV | |||
VOL | Output low voltage | –150 | 150 | mV | ||
tSK | Output-to-output skew | Same post divider, output divide values, and output type | 100 | ps | ||
dV/dt | Output slew rate(13) | ±150mV around center point, fOUT ≤ 400MHz | 1.6 | 4 | V/ns | |
PNFLOOR | Output phase noise floor (fOFFSET > 10MHz) | 100MHz | –160 | dBc/Hz | ||
ODC | Output duty cycle(10) | 45 | 55 | % | ||
1.8V LVCMOS OUTPUT CHARACTERISTICS | ||||||
fOUT | Output frequency | OUT4, OUT5, OUT6 or OUT7 | 1E–6 | 200 | MHz | |
VOH | Output high voltage | IOH = 1mA | 1.2 | V | ||
VOL | Output low voltage | IOL = 1mA | 0.4 | V | ||
IOH | Output high current | –23 | mA | |||
IOL | Output low current | 20 | mA | |||
tR/tF | Output rise/fall time | 20% to 80% | 250 | ps | ||
tSK | Output-to-output skew | Same post divider, output divide values, and output type | 100 | ps | ||
Output-to-output skew | Same post divider, output divide values, LVCMOS-to-DIFF | 1.5 | ns | |||
PNFLOOR | Output phase noise floor | fOUT = 66.66MHz; fOFFSET > 10MHz | -160 | dBc/Hz | ||
ODC | Output duty cycle(10) | 45 | 55 | % | ||
ROUT | Output impedance | 50 | Ω | |||
3-LEVEL LOGIC INPUT CHARACTERISTICS (HW_SW_CTRL, GPIO1, REFSEL, STATUS[1:0]) | ||||||
VIH | Input high voltage | 1.4 | V | |||
VIM | Input mid voltage | Input floating with internal bias and PDN pulled low | 0.7 | 0.9 | V | |
VIL | Input low voltage | 0.4 | V | |||
IIH | Input high current | VIH = VDD | –40 | 40 | µA | |
IIL | Input low current | VIL = GND | –40 | 40 | µA | |
2-LEVEL LOGIC INPUT CHARACTERISTICS (PDN, GPIO[2:0], SDI, SCK, SCS) | ||||||
VIH | Input high voltage | 1.2 | V | |||
VIL | Input low voltage | 0.6 | V | |||
IIH | Input high current | VIH = VDD | -40 | 40 | µA | |
IIL | Input low current | VIL = GND | -40 | 40 | µA | |
LOGIC OUTPUT CHARACTERISTICS (STATUS[1:0], SDO) | ||||||
VOH | Output high voltage | IOH = 1mA | 2.4 | V | ||
VOL | Output low voltage | IOL = 1mA | 0.4 | V | ||
tR/tF | Output rise/fall time | 20% to 80%, LVCMOS mode, 1kΩ to GND | 500 | ps | ||
SPI TIMING REQUIREMENTS (SDI, SCK, SCS, SDO) | ||||||
fSCK | SPI clock rate | 20 | MHz | |||
SPI clock rate; NVM write | 5 | MHz | ||||
t1 | SCS to SCK setup time | 10 | ns | |||
t2 | SDI to SCK setup time | 10 | ns | |||
t3 | SDI to SCK hold time | 10 | ns | |||
t4 | SCK high time | 25 | ns | |||
t5 | SCK low time | 25 | ns | |||
t6 | SCK to SDO valid read-back data | 20 | ns | |||
t7 | SCS pulse width | 20 | ns | |||
t8 | SDI to SCK hold time | 10 | ns | |||
I2C-COMPATIBLE INTERFACE CHARACTERISTICS (SDA, SCL) | ||||||
VIH | Input high voltage | 1.2 | V | |||
VIL | Input low voltage | 0.6 | V | |||
IIH | Input leakage | –15 | 15 | µA | ||
VOL | Output low voltage | IOL = 3mA | 0.3 | V | ||
fSCL | I2C clock rate | Standard | 100 | kHz | ||
Fast mode | 400 | |||||
tSU(START) | START condition setup time | SCL high before SDA low | 0.6 | µs | ||
tH(START) | START condition hold time | SCL low after SDA low | 0.6 | µs | ||
tW(SCLH) | SCL pulse width high | 0.6 | µs | |||
tW(SCLL) | SCL pulse width low | 1.3 | µs | |||
tSU(SDA) | SDA setup time | 100 | ns | |||
tH(SDA) | SDA hold time | SDA valid after SCL low | 0 | µs | ||
tR(IN) | SDA/SCL input rise time | 300 | ns | |||
tF(IN) | SDA/SCL input fall time | 300 | ns | |||
tF(OUT) | SDA output fall time | CBUS ≤ 400pF | 300 | ns | ||
tSU(STOP) | STOP condition setup time | 0.6 | µs | |||
tBUS | Bus free time between STOP and START | 1.3 | µs | |||
POWER SUPPLY NOISE REJECTION (PSNR) / CROSSTALK SPURS | ||||||
PSNR50mV | Spur induced by power supply noise (VN = 50mVpp) (6)(7) | VDD = 3.3V, VDDO_x = 3.3V, 156.25MHz, AC-DIFF output | –83 | dBc | ||
VDD = 3.3V, VDDO_x = 3.3V, 156.25MHz, HCSL output | –78 | dBc | ||||
VDD = 3.3V, VDDO_x = 2.5V, 156.25MHz, AC-DIFF output | -73 | dBc | ||||
VDD = 3.3V, VDDO_x = 2.5V, 156.25 MHz, HCSL output | -68 | dBc | ||||
PSNR25mV | Spur induced by power supply noise (VN = 25mVpp)(6)(7) | VDD = 3.3V, VDDO_x = 1.8V, 156.25MHz, AC-DIFF output | –63 | dBc | ||
VDD = 3.3V, VDDO_x = 1.8V, 156.25MHz, HCSL output | –58 | dBc | ||||
VDD = 3.3V, VDDO_x = 1.8V, 156.25MHz, LVCMOS output | –45 | dBc | ||||
SPURXTALK | Spur level due to output-to-output crosstalk (adjacent channels)(7) | fOUTx = 156.25MHz, fOUTy = 155.52MHz, AC | –75 | dBc | ||
PLL CLOCK OUTPUT PERFORMANCE CHARACTERISTICS | ||||||
RJ | RMS Phase Jitter (12kHz to 20MHz) | 625MHz AC-DIFF output from APLL1, fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz | 50 | 80 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) | 625MHz AC-DIFF output from APLL1, fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz. fVCO1 = 2.5GHz; VDDO = 3.3V, power supply ripple VN ≤ 50mV, 100kHz ≤ FN ≤ 10MHz | 55 | 100 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) | 312.5MHz AC-DIFF output from APLL1, fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz | 50 | 80 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) | 312.5MHz AC-DIFF output from APLL1, fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz. fVCO1 = 2.5GHz; VDDO = 3.3V, power supply ripple VN ≤ 50mV, 100kHz ≤ FN ≤ 10MHz | 55 | 110 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) | 156.25MHz AC-LVPECL output from APLL1, fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz | 60 | 90 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) | 156.25MHz AC-LVPECL output from APLL1, fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz; VDDO = 3.3V, power supply ripple ≤ 50mV, 100kHz ≤ FN ≤ 10MHz | 65 | 135 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) excluding ouput crosstalk spurs | 155.52MHz AC-LVPECL output from APLL2 at OUT4, OUT5, OUT6 and OUT7. 156.25MHz from APLL1 at all other outputs. fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz, fPD2 = fVCO1/18, fVCO2 = 5.59872GHz | 125 | 200 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) | 155.52MHz AC-LVPECL output from APLL2 at OUT4, OUT5, OUT6 and OUT7. 156.25MHz from APLL1 at all other outputs. fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz, fPD2 = fVCO1/18, fVCO2 = 5.59872GHz | 145 | fs RMS | ||
RJ | RMS Phase Jitter (12kHz to 20MHz) excluding output crosstalk spurs | 153.6MHz AC-LVPECL output from APLL2 at OUT4, OUT5, OUT6 and OUT7. 156.25MHz from APLL1 at all other outputs. fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz, fPD2 = fVCO1/18, fVCO2 = 5.5296GHz | 125 | 200 | fs RMS | |
RJ | RMS Phase Jitter (12kHz to 20MHz) | 153.6MHz AC-LVPECL output from APLL2 at OUT4, OUT5, OUT6 and OUT7. 156.25MHz from APLL1 at all other outputs. fXO = 48MHz, fPD1 = fXO/2, fVCO1 = 2.5GHz, fPD2 = fVCO1/18, fVCO2 = 5.5296GHz | 150 | fs RMS | ||
BW | DPLL bandwidth range(8) | Programmed bandwidth setting | 0.01 | 4000 | Hz | |
JPK | DPLL closed-loop jitter peaking(11) | fREF = 25MHz, fOUT = 10MHz, DPLL BW = 0.1Hz or 10Hz | 0.1 | dB | ||
JTOL | Jitter tolerance | Jitter modulation = 10Hz, 25.78125Gbps | 6455 | UI p-p | ||
tHITLESS | Phase hit between two reference inputs with 0ppm error | Valid for a single switchover event between two clock inputs at the same frequency | ± 50 | ps | ||
fHITLESS | Frequency transient during hitless switch | Valid for a single switchover event between two clock inputs at the same frequency | ± 10 | ppb |