In a typical application, consider the following design requirements or parameters to implement the overall clock solution:
- Device initial configuration: Configure the device as either host programmed (MCU or FPGA) or factory pre-programmed.
- Device start-up mode and serial interface: Typically, this is EEPROM +
I2C or SPI mode.
- XO frequency, signal type, and frequency accuracy and stability: Consider a high-stability TCXO or OCXO for the XO input if any of the following is required:
- Standard-compliant frequency stability (such as SyncE, SONET/SDH, IEEE 1588)
- Lowest possible close-in phase noise at offsets ≤ 100Hz
- Narrow DPLL bandwidth ≤ 10Hz
- For the DPLL/APLL1 domain, determine the following:
- Input clocks: frequency, buffer mode, priority, and input selection mode
- Output clocks: frequency, buffer mode
- DPLL loop bandwidth and maximum TDC frequency
- If the DCO Mode is required
- For the APLL2 domain, determine the following:
- APLL2 reference: VCO1 for synchronous clocking with Cascaded APLL2, or XO for asynchronous clocking with Non-cascaded APLL2
- Output clocks: frequency, buffer mode
- Input clock and PLL monitoring options
- Status outputs and interrupt flag
- Power supply rails