JAJSKL8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
The SN65LVDS302 is a de-serialising device where the input serial data and clock are received through Sub Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS302 supports three operating power modes (Shutdown, Standby, and Active) to conserve power.
Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used to put the SN65LVDS302 in a Shutdown mode. The SN65LVDS302 enters an active Standby mode if the common mode voltage of the CLK input becomes shifted to VDDLVDS, as when the transmitter releases the CLK output into high-impedance. This minimizes power consumption without the need of switching an external control pin. The SN65LVDS302 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with VDD = 0 V. This feature allows signal power-up before VCC is stabilized.
When receiving, the PLL locks to the incoming clock (CLK) and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The de-serialized data is presented on the parallel output bus with a recreation of the Pixel clock (PCLK) generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK and DE held low, while all other parallel outputs are pulled high.
The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load designs.