JAJSKL8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
When the SN65LVDS302 is enabled and a SubLVDS clock input present, the PLL pursues lock to the input clock. While the PLL pursues lock the output data bus holds a static output pattern:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.
For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than fPCLK(min), the SN65LVDS302 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL deadlock (loss of VCO oscillation).