JAJSKL8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-61A10D85-4F49-4EE3-94EE-31BB745CFFC8-low.svgFigure 5-1 ZXH Package80-Pin nFBGATop View
Table 5-1 Pin Functions
PIN DESCRIPTION
NAME NO. I/O
CMOS
B0 to B7 See (1) CMOS Out Blue pixel data
G0 to G7 See (1) CMOS Out Green pixel data
R0 to R7 See (1) CMOS Out Red pixel data
CPE J9 CMOS Out Channel parity error

This output indicates the detection of a parity error by generating an output high-pulse for half of a PCLK clock cycle; this allows counting parity errors with a simple counter.

0: no error

high-pulse: bit error detected
CPOL H1 CMOS In

Output clock polarity selection:

0: rising edge clocking

1: falling edge clocking
DE J8 CMOS Out Data Enable
F/S G8 CMOS In

CMOS bus rise time select:

1: fast output rise time

0: slow output rise time
HS H9 CMOS Out Horizontal sync
LS0 C1 CMOS In Link select: determines active SubLVDS Data Links and PLL Range) (see Table 8-1)
LS1 D2
PCLK G9 CMOS Out Output Pixel Clock; rising or falling clock polarity is selected by control input CPOL
RXEN J7 CMOS In

Disables the CMOS Drivers and turns off the PLL, putting device in shutdown mode.(2)

1: Receiver enabled

0: Receiver disabled (shutdown)
SWAP J2 CMOS In

Bus swap: swaps the bus pins to allow device placement on top or bottom of PCB. See pinout drawing and Table 5-2 for pin assignments.

0: data output from R7 to B0

1: data output from B0 to R7
VS H8 CMOS Out Vertical sync
SUBLVDS
CLK+, CLK– J3, J4 SubLVDS In SubLVDS input pixel clock (polarity is fixed)
D0+, D0– J5, J6 SubLVDS In SubLVDS data link (active during normal operation)
D1+, D1– F1, G1 SubLVDS In SubLVDS data link (active during normal operation when LS0 = high and LS1 = low, or LS0 = low and LS1 = high; high impedance if LS0 = LS1 = low); input can be left open if unused.
D2+, D2– D1, E1 SubLVDS In SubLVDS data link (active during normal operation when LS0 = low and LS1 = high, high-impedance when LS1 = low); input can be left open if unused.
POWER SUPPLY
VDD C2, C4, C6,
D7 to G7		 Power Supply Supply voltage
VDDLVDS H2, H5 Power Supply SubLVDS I/O supply voltage
VDDPLLA H3 Power Supply PLL analog supply voltage
VDDPLLD F2 Power Supply PLL digital supply voltage
GND A1, A9, C5, C7,
D3 to D6, E3 to E6,
F3 to F6,
G3 to G6, H7		 Ground Supply ground
GNDLVDS G2, H6, J1 Ground SubLVDS ground
GNDPLLA H4 Ground PLL analog ground
GNDPLLD E2 Ground PLL digital ground
(1) Pin assignment depends on SWAP pin setting. Swappable pins are detailed in Table 5-2.
(2) RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input must be pulled low for longer than 10 µs continuously to force the receiver to enter Shutdown. The input must be pulled high for at least 10 μs continuously to activate the receiver. An input pulse shorter than 5 µs is interpreted as glitch and becomes ignored. At power up, the receiver is enabled immediately if RXEN = H and disabled if RXEN = L.
Table 5-2 Swappable Pins
SIGNAL SWAP(1) PIN SIGNAL SWAP(1) PIN SIGNAL SWAP(1) PIN
B0 L F9 G0 L B9 R0 L A5
H B1 H B5 H C8
B1 L F8 G1 L B8 R1 L B4
H A2 H A6 H C9
B2 L E9 G2 L A8 R2 L A4
H B2 H B6 H D8
B3 L E8 G3 L B7 R3 L B3
H A3 H A7 H D9
B4 L D9 G4 L A7 R4 L A3
H B3 H B7 H E8
B5 L D8 G5 L B6 R5 L B2
H A4 H A8 H E9
B6 L C9 G6 L A6 R6 L A2
H B4 H B8 H F8
B7 L C8 G7 L B5 R7 L B1
H A5 H B9 H F9
(1) The SWAP pin is either set to GND (L) or VDD (H).