JAJSKL8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2 Typical IC Power Consumption Test Pattern

Typical power-consumption test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit receive words in 2-channel mode and five 30-bit receive words in 3-channel mode. The pattern repeats itself throughout the entire measurement. It is assumed that every possible code on the RGB outputs has the same probability to occur during typical device operation.

Table 7-2 Typical IC Power Consumption Test Pattern, 1-Channel Mode
WORDTEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
10x0000007
20xFFF0007
30x01FFF47
40xF0E07F7
50x7C3E1E7
60xE707C37
70xE1CE6C7
80xF1B9237
90x91BB347
100xD4CCC67
110xAD53377
120xACB2207
130xAAB2697
140x5556957
150xAAAAAB3
160xAAAAAA5
Table 7-3 Typical IC Power Consumption Test Pattern, 2-Channel Mode
WORDTEST PATTERN:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
10x0000001
20x03F03F1
30xBFFBFF1
40x1D71D71
50x4C74C71
60xC45C451
70xA3aA3A5
80x5555553
Table 7-4 Typical IC Power Consumption Test Pattern, 3-Channel Mode
WORDTest Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE
10xFFFFFF1
20x0000001
30xF0F0F01
40xCCCCCC1
50xAAAAAA7